Predictable and efficient virtual addressing for safety-critical real-time systems

Proceedings - Euromicro Conference on Real-Time Systems

Volumn , Issue , 2001, Pages 183-190

  Bennett, M D ^a   Audsley, N C ^a  

^a Dept of Computer Science   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRITY LEVELS; POWERPC; SAFETY CRITICAL SYSTEMS; TIMING ANALYSIS; VIRTUAL MEMORY; VIRTUAL MEMORY SYSTEMS; WORST-CASE ANALYSIS;

ARM PROCESSORS; COMMERCE; MEMORY MANAGEMENT UNITS; SAFETY ENGINEERING;

REAL TIME SYSTEMS;

EID: 26444587616     PISSN: 10683070     EISSN: None     Source Type: Journal    
DOI: 10.1109/EMRTS.2001.934028     Document Type: Article

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