Performance of omega-shaped-gate silicon nanowire MOSFET with diameter down to 8 nm

IEEE Electron Device Letters

Volumn 33, Issue 11, 2012, Pages 1526-1528

  Barraud, S ^a   Coquand, R ^a,b   Casse, M ^a   Koyama, M ^a,c   Hartmann, J M ^a   Maffini Alvaro, V ^a   Comboroure, C ^a   Vizioz, C ^a   Aussenac, F ^a   Faynot, O ^a   Poiroux, T ^a  

^a CEA LETI   (France)

^b STMICROELECTRONICS   (France)

^c TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

Electrostatic confinement; MOSFET; nanowire (NW); omega gate; scalability; trigate (TG)

Indexed keywords

ELECTRICAL PERFORMANCE; ELECTROSTATIC CONFINEMENT; ELECTROSTATIC CONTROL; ESSENTIAL CONSIDERATIONS; MOS-FET; MOSFETS; OMEGA-GATE; OMEGA-SHAPED-GATES; SHORT-CHANNEL PERFORMANCE; SILICON NANOWIRES; SPACER THICKNESS; TRIGATE;

ELECTROSTATIC DEVICES; ELECTROSTATICS; NANOWIRES; SCALABILITY; SILICON NITRIDE;

MOSFET DEVICES;

EID: 84867896956     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2012.2212691     Document Type: Article

References (14)

1. K. Tachi, M. Cassé, S. Barraud, C. Dupré, A. Hubert, N. Vulliet, M. E. Faivre, C. Vizioz, C. Carabasse, V. Delaye, J. M. Hartmann, H. Iwai, S. Cristoloveanu, O. Faynot, and T. Ernst, "Experimental study on carrier transport limiting phenomena in 10nm width nanowire CMOS transistors," in IEDM Tech. Dig., 2010, pp. 34.4.1-34.4.4.
2. M. Li, K. H. Yeo, S. D. Suk, Y. Y. Yeoh, D.-W. Kim, T. Y. Chung, K. S. Oh, and W.-S. Lee, "Sub-10 nm gate-all-around CMOS nanowire transistors on bulk Si substrate," in VLSI Symp. Tech. Dig., 2009, pp. 94-95.
3. D.-W. Kim, M. Li, K.-H. Yeo, Y.-Y. Yeoh, S.-D. Suk, K.-H. Cho, K. Oh, and W.-S. Lee, "Twin silicon nanowire FET (TSNWFET) on SOI with 8 nm silicon nanowires and 25 nm surrounding TiN gate," in Proc. IEEE Int. SOI Conf., 2008, pp. 117-118.
4. Y. Jiang, N. Singh, T. Y. Liow, P. C. Lim, S. Tripathy, G. Q. Lo, D. S. H. Chan, and D.-L. Kwong, "Omega-gate p-MOSFET with nanowirelike SiGe/Si core/shell channel," IEEE Electron Device Lett., vol. 30, no. 4, pp. 392-394, Apr. 2009.
5. F.L. Yang, H.-Y. Chen, F.-C. Chen, C.-C. Huang, C.-Y. Chang, H.-K. Chiu, C.-C. Lee, C.-C. Chen, H.-T. Huang, C.-J. Chen, H. J. Tao, Y.-C. Yeo, M.-S. Liang, and C. Hu, "25 nm CMOS omega FETs," in IEDM Tech. Dig., 2002, pp. 255-258.
6. C. Jahan, O. Faynot, M. Cassé, R. Ritzenthaler, L. Brévard, L. Tosti, X. Garros, C. Vizioz, F. Allain, A. M. Papon, H. Dansas, F. Martin, M. Vinet, B. Guillaumot, A. Toffoli, B. Giffard, and S. Deleonibus, "ΩFETs transistors with TiN metal gate and HfO2 down to 10 nm," in VLSI Tech. Dig., 2005, pp. 112-113.
7. T. Burchhart, C. Zeiner, Y. J. Hyun, A. Lugstein, G. Hochleitner, and E. Bertagnolli, "High performance Ω-gated Ge nanowire MOSFET with quasi-metallic source/drain contacts," Nanotechnology, vol. 21, no. 43, pp. 435 704-435 708, Oct. 2010.
8. M. Saitoh, Y. Nakabayashi, K. Ota, K. Uchida, and T. Numata, "Understanding of short-channel mobility in tri-gate nanowire MOSFETs and enhanced stress memorization technique for performance improvement," in IEDM Tech. Dig., 2010, pp. 34.3.1-34.3.4.
9. R. Coquand, S. Barraud, M. Cassé, P. Leroux, C. Vizioz, C. Comboroure, P. Perreau, E. Ernst, M.-P. Sanson, V. Maffini-Alvaro, C. Tabone, S. Barnola, D. Munteanu, G. Ghibaudo, S. Monfray, F. Boeuf, and T. Poiroux, "Scaling of high-k/metal-gate trigate SOI nanowire transistors down to 10 nm width," in Proc. ULIS Conf., 2012, pp. 37-40.
10. M. Bescond, K. Nehari, J. L. Autran, N. Cavassilas, D. Munteanu, and M. Lannoo, "3D quantum modeling and simulation of multiple-gate nanowire MOSFETs," in IEDM Tech. Dig., 2004, pp. 617-620.
11. M. Shin, "Quantum simulation of device characteristics of silicon nanowire FETs," IEEE Trans. Nanotechnol., vol. 6, no. 2, pp. 230-237, Mar. 2007.
12. C.-W. Lee, S.-R.-N. Yun, C.-G. Yu, J.-T. Park, and J.-P. Colinge, "Device design guidelines for nano-scale MuGFETs," Solid State Electron., vol. 51, no. 3, pp. 505-510, Mar. 2007.
13. I. Ferain, C. A. Colinge, and J.-P. Colinge, "Multigate transistors as the future of classical metal-oxide-semiconductor field-effect transistors," Nature, vol. 479, no. 7373, pp. 310-316, Nov. 2011.
14. S. Bangsaruntip, G. M. Cohen, A. Majumdar, and J. W. Sleight, "Universality of short-channel effects in undoped-body silicon nanowire MOSFETs," IEEE Electron Device Lett., vol. 31, no. 9, pp. 903-905, Sep. 2010.