Scaling of high-κ/metal-gate trigate SOI nanowire transistors down to 10nm width

2012 13th International Conference on Ultimate Integration on Silicon, ULIS 2012

Volumn , Issue , 2012, Pages 37-40

  Coquand, R ^a,b,c   Barraud, S ^a   Casse M ^a   Leroux, P ^a,d   Vizioz, C ^a   Comboroure, C ^b   Perreau, P ^a   Ernst, E ^a   Samson, M P ^b   Maffini Alvaro, V ^a   Tabone, C ^a   Barnola, S ^a   Munteanu, D ^d   Ghibaudo, G ^c   Monfray, S ^b   Boeuf, F ^b   Poiroux, T ^a  

^a CEA LETI   (France)

^b STMICROELECTRONICS   (France)

^c IMEP LAHC   (France)

^d AIX MARSEILLE UNIVERSITÉ   (France)

Author keywords

Carrier mobility; Scalability; Tri Gate SOI Nanowire

Indexed keywords

ELECTRICAL PERFORMANCE; ELECTROSTATIC INTEGRITY; NANOWIRE TRANSISTORS; PLANAR DEVICES; SHORT-CHANNEL DEVICES; TOP SURFACE; TRIGATE;

CARRIER MOBILITY; ELECTROSTATIC DEVICES; SCALABILITY; TRANSPORT PROPERTIES;

NANOWIRES;

EID: 84861217393     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ULIS.2012.6193351     Document Type: Conference Paper

References (13)

1. C.Dupré et al IEDM Tech. Dig., p.749, 2008
2. K.Tachi et al Si Nanoelec. Worshop, p.11, 2009
3. M. Saitoh et al., Symp. VLSI Tech, p.169, 2010
4. G. Bidal et al., Symp. VLSI Tech, p.240, 2009
5. S. D. Suk et al IEDM Tech. Dig., p.717, 2005
6. K. Tachi et al. IEDM Tech. Dig., p41, 2010
7. M. Li et al., Symp. VLSI Tech, p.94, 2009
8. S. Bangsaruntip et al., Symp. VLSI Tech, p.978, 2010
9. S. D. Suk et al IEDM Tech. Dig., p.891, 2007
10. J. Chen et al., Symp. VLSI Tech, p.175, 2010
11. L. Zhang et al., Symp. VLSI Tech, p.46, 2009
12. J. Chen et al., Symp. VLSI Tech, p.32, 2008
13. T. Signamarcheix et al., EuroSOI, 2010