NVMain: An architectural-level main memory simulator for emerging non-volatile memories

Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012

Volumn , Issue , 2012, Pages 392-397

  Poremba, Matt ^a   Xie, Yuan ^a,b  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

^b AMD Research China Lab   (China)

Author keywords

emerging memory technology; memory architecture

Indexed keywords

COMPUTER ARCHITECTS; COMPUTING SYSTEM; DESIGN POINTS; DESIGN SPACE EXPLORATION; EMERGING NON-VOLATILE MEMORIES; EMERGING NON-VOLATILE MEMORY TECHNOLOGY; MAIN MEMORY; MEMORY TECHNOLOGY;

COMPUTER SYSTEMS; DATA STORAGE EQUIPMENT; DESIGN; DYNAMIC RANDOM ACCESS STORAGE; SIMULATORS; TECHNOLOGY;

MEMORY ARCHITECTURE;

EID: 84867774220     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2012.82     Document Type: Conference Paper

References (19)

1. ITRS, "International technology roadmap for semiconductors," in http://www.itrs.net/reports.html, 2009.
2. B. Jacob, The Memory System: You Can't Avoid It, You Can't Ignore It, You Can't Fake It. Morgan and Claypool, 2009.
3. Y. Xie, G. H. Loh, B. Black, and K. Bernstein, "Design space exploration for 3d architectures," J. Emerg. Technol. Comput. Syst., pp. 65-103, Apr. 2006.
4. G. H. Loh, "3d-stacked memory architectures for multi-core processors," in Proceedings of the 35th Annual International Symposium on Computer Architecture, 2008, pp. 453-464.
5. J. Mogul, E. Argollo, M. Shah, and P. Faraboschi, "Operating system support for nvm+dram hybrid main memory," in HotOS 2009, 2009.
6. M. Qureshi, V. Srinivasan, and J. A. Rivers, "Scalable high performance main memory system using phase-change memory technology," in Proc. of the 36th Int'l Symposium on Computer Architecture, 2009.
7. M. K. Qureshi, M. M. Franceschini, and L. A. Lastras-montao, "Improving read performance of phase change memories via write cancellation and write pausing," in Proceedings 16th International Symposium on High-Performance Computer Architecture, 2010.
8. B. Lee, E. Ipek, O. Mutlu, and D. Burger, "Architecting phase change memory as a scalable dram alternative," in Proceedings of the 36th International Symposium on Computer Architecture, 2009.
9. P. Zhou, B. Zhao, J. Yang, and Y. Zhang, "A durable and energy efficient main memory using phase change memory technology," in Proceedings of the 36th International Symposium on Computer Architecture, 2009.
10. N. H. Seong, H. D. Woo, V. Srinivasan, J. A. Rivers, and H. Lee, "Safer: Stuck-at-fault error recovery for memories," in The 43rd Annaul IEEE/ACM International Symposium on Microarchitecture, 2010.
11. E. Ipek, J. Condit, E. Nightingale, D. Burger, and T. Moscibroda, "Dynamically replicated memory: Building reliable systems from nanoscale resistive memories," in ASPLOS 2010, 2010.
12. A. Udipi, N. Muralimanohar, and et. al., "Combining memory and a controller with photonics through 3d-stacking to enable scalable and energy-efficient systems," in Proceedings of the 38th International Symposium on Computer Architecture, 2011.
13. D. Wang, B. Ganesh, N. Tuaycharoen, K. Baynes, A. Jaleel, and B. Jacob, "Dramsim: a memory system simulator," in ACM SIGARCH Computer Architecture News, 2005.
14. MICRON. Calculating memory system power for ddr3. [Online]. Available: http://www.micron.com/
15. X. Dong, N. Jouppi, and Y. Xie, "Nvsim: A circuit-level performance, energy, and area model for emerging nonvolatile memory," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2012, pp. 994-1007.
16. B. Jacob, S. Ng, and D. Wang, Memory Systems: Cache, DRAM, Disk. Elsevier, 2008.
17. S. Cho and H. Lee, "Flip-n-write: A simple deterministic technique to improve pram write performance, energy and endurance," in MICRO 2009, 2009.
18. N. L. Binkert, R. G. Dreslinski, L. R. Hsu, K. T. Lim, A. G. Saidi, and S. K. Reinhardt, "The m5 simulator: Modeling networked systems," IEEE Micro, vol. 26, pp. 52-60, 2006.
19. K. Tsuchida, T. Inaba, K. Fujita, Y. Ueda, T. Shimizu, Y. Asao, T. Kajiyama, M. Iwayama, K. Sugiura, S. Ikegawa, T. Kishi, T. Kai, M. Amano, N. Shimomura, H. Yoda, and Y. Watanabe, "A 64mb mram with clamped-reference and adequate-reference schemes." in ISSCC. IEEE, 2010, pp. 258-259.