Workload and power budget partitioning for single-chip heterogeneous processors

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2012, Pages 401-410

  Wang, Hao ^a   Sathish, Vijay ^a   Singh, Ripudaman ^a   Schulte, Michael J ^b   Kim, Nam Sung ^a  

^a UNIVERSITY OF WISCONSIN MADISON   (United States)

^b ADVANCED MICRO DEVICES   (United States)

Author keywords

Power constraint; Single chip heterogeneous processor; Voltage Frequency Core scaling

Indexed keywords

CHIP POWER; COMPUTING SYSTEM; EMERGING APPLICATIONS; EXHAUSTIVE SEARCH ALGORITHMS; HETEROGENEOUS PROCESSORS; JOINT OPTIMIZATION; MAXIMUM THROUGH-PUT; OPTIMAL COMBINATION; POWER BUDGETS; POWER CONSTRAINTS; POWER EFFICIENCY; RUNTIMES; SINGLE CHIPS; SINGLE-CHIP; TECHNOLOGY SCALING; THROUGHPUT IMPROVEMENT;

BUDGET CONTROL; OPTIMIZATION; PARALLEL ARCHITECTURES; THROUGHPUT;

ALGORITHMS;

EID: 84867536119     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2370816.2370873     Document Type: Conference Paper

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