Improving throughput of power-constrained GPUs using dynamic voltage/frequency and core scaling

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2011, Pages 111-120

  Lee, Jungseob ^a   Sathisha, Vijay ^a   Schulte, Michael ^b   Compton, Katherine ^a   Kim, Nam Sung ^a  

^a University of Wisconsin Madison   (United States)

^b ADVANCED MICRO DEVICES   (United States)

Author keywords

Dynamic voltage, frequency, and core scaling; GPU; Power constraint; Throughput

Indexed keywords

DYNAMIC VOLTAGE; GPU; GRAPHIC PROCESSING UNITS; INTEGRATED CORE; OFF-CHIP MEMORIES; ON-CHIP INTERCONNECTS; PARALLEL APPLICATION; POWER CONSTRAINTS; RUNTIMES;

IMAGE CODING; PARALLEL ARCHITECTURES; PROGRAM PROCESSORS;

THROUGHPUT;

EID: 84863037228     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.2011.17     Document Type: Conference Paper

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