Exploiting core working sets to filter the L1 cache with random sampling

IEEE Transactions on Computers

Volumn 61, Issue 11, 2012, Pages 1535-1550

  Etsion, Yoav ^a   Feitelson, Dror G ^b  

^a TECHNION ISRAEL INSTITUTE OF TECHNOLOGY   (Israel)

^b HEBREW UNIVERSITY OF JERUSALEM   (Israel)

Author keywords

Benchmark testing; cache filtering; cache insertion policy; Core working sets; dual cache design; Educational institutions; Histograms; L1 cache; mass count disparity; Measurement; Power demand; Probabilistic logic; random insertion policy; System performance

Indexed keywords

BENCHMARK TESTING; CACHE FILTERING; EDUCATIONAL INSTITUTIONS; HISTOGRAMS; L1 CACHE; MASS-COUNT DISPARITY; POWER DEMANDS; RANDOM INSERTIONS; SYSTEM PERFORMANCE; WORKING SET;

DESIGN; MEASUREMENTS; PROBABILISTIC LOGICS;

CACHE MEMORY;

EID: 84867291675     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2011.197     Document Type: Article

References (34)

1. T. Austin, E. Larson, and D. Ernst, "SimpleScalar: An Infrastructure for Computer System Modeling," Computer, vol. 35, no. 2, pp. 59-67, Feb. 2002.
2. M. Behar, A. Mendelson, and A. Kolodny, "Trace Cache Sampling Filter," Proc. Int'l Conf. Parallel Architectures and Compilation Techniques (PACT), pp. 255-264, Sept. 2005. (Pubitemid 44159745)
3. L.A. Belady, "A Study of Replacement Algorithms for a Virtual-Storage Computer," IBM Systems J., vol. 5, no. 2, pp. 78-101, 1966.
4. M. Brehob, S. Wagner, E. Torng, and R. Enbody, "Optimal Replacement Is NP-Hard for Nonstandard Caches," IEEE Trans. Computers, vol. 53, no. 1, pp. 73-76, Jan. 2004.
5. K.K. Chan, C.C. Hay, J.R. Keller, G.P. Kurpanek, F.X. Schumacher, and J. Zheng, "Design of the HP PA 7200 CPU," Hewlett-Packard J., vol. 47, no. 1, pp. 25-33, Feb. 1996. (Pubitemid 126765556)
6. S. Cho, P.C. Yew, and G. Lee, "Decoupling Local Variable Accesses in a Wide-Issue Superscalar Processor," Proc. Int'l Symp. Computer Architecture (ISCA), pp. 100-110, 1999.
7. P.J. Denning, "The Working Set Model for Program Behavior," Comm. ACM, vol. 11, no. 5, pp. 323-333, May 1968.
8. P.J. Denning and S.C. Schwartz, "Properties of the Working-Set Model," Comm. ACM, vol. 15, no. 3, pp. 191-198, Mar. 1972.
9. D.R. Ditzel and H.R. McLellan, "Register Allocation for Free: The C Machine Stack Cache," Proc. Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS), pp. 48-56, 1982.
10. Y. Etsion, "The Skewed Distribution of Working Sets: Leveraging Randomness for Cache Design," PhD thesis, School of Computer Science and Eng., Hebrew Univ., Oct. 2008.
11. Y. Etsion and D.G. Feitelson, "L1 Cache Filtering through Random Selection of Memory References," Proc. Int'l Conf. Parallel Architecture and Compilation Techniques (PACT), pp. 235-244, Sept. 2007.
12. Y. Etsion and D.G. Feitelson, "Probabilistic Prediction of Temporal Locality," IEEE Computer Architecture Letters, vol. 6, no. 1, pp. 17-20, Jan.-June 2007.
13. D.G. Feitelson, "Metrics for Mass-Count Disparity," Proc. IEEE Int'l Symp. Modeling, Analysis, and Simulation of Computer and Telecomm. Systems (MASCOTS), pp. 61-68, Sept. 2006.
14. A. Jaleel, K.B. Theobald, S.C. Steely Jr., and J. Emer, "High Performance Cache Replacement Using Re-Reference Interval Prediction (RRIP)," Proc. Int'l Symp. Computer Architecture (ISCA), pp. 60-71, 2010.
15. S. Jin and A. Bestavros, "Sources and Characteristics of Web Temporal Locality," Proc. Int'l Symp. Modeling, Analysis, and Simulation of Computer and Telecomm. Systems (MASCOTS), pp. 28-35, Aug. 2000.
16. T.L. Johnson, D.A. Connors, M.C. Merten, and W.-M.W. Hwu, "Run-Time Cache Bypassing," IEEE Trans. Computers, vol. 48, no. 12, pp. 1338-1354, Dec. 1999. (Pubitemid 30553392)
17. N.P. Jouppi, "Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers," Proc. Int'l Symp. Computer Architecture (ISCA), pp. 364-373, 1990.
18. H.H.S. Lee, M. Smelyanskiy, G.S. Tyson, and C.J. Newburn, "Stack Value File: Custom Microarchitecture for the Stack," Proc. Int'l Symp. High-Performance Computer Architecture (HPCA), pp. 5-14, 2001. (Pubitemid 32873573)
19. M.O. Lorenz, "Methods of Measuring the Concentration of Wealth," Publications of the Am. Statistical Assoc., vol. 9, no. 70, pp. 209-219, June 1905.
20. S. McFarling, "Cache Replacement with Dynamic Exclusion," Proc. Int'l Symp. Computer Architecture (ISCA), pp. 191-200, 1992. (Pubitemid 23579900)
21. N. Megiddo and D.S. Modha, "ARC: A Self-Tuning, Low Overhead Replacement Cache," Proc. USENIX Conf. File and Storage Technologies (FAST), 2003.
22. G.-H. Park, K.-W. Lee, J.-H. Lee, T.-D. Han, and S.-D. Kim, "A Power Efficient Cache Structure for Embedded Processors Based on the Dual Cache Structure," Proc. Workshop Languages, Compilers, and Tools for Embedded Systems (LCTES), pp. 162-177, 2000. (Pubitemid 33250003)
23. M.K. Qureshi, A. Jaleel, Y.N. Patt, S.C. Steely, and J. Emer, "Adaptive Insertion Policies for High Performance Caching," Proc. Int'l Symp. Computer Architecture (ISCA), pp. 381-391, 2007. (Pubitemid 47582119)
24. M.K. Qureshi, D.N. Lynch, O. Mutlu, and Y.N. Patt, "A Case for MLP-Aware Cache Replacement," Proc. Int'l Symp. Computer Architecture (ISCA), pp. 167-178, June 2006.
25. K. Rajan and G. Ramaswamy, "Emulating Optimal Replacement with a Shepherd Cache," Proc. Ann. IEEE/ACM Int'l Symp. Microarchitecture, pp. 445-454, 2007.
26. J.A. Rivers and E.S. Davidson, "Reducing Conflicts in Direct-Mapped Caches with a Temporality-Based Design," Proc. Int'l Conf. Parallel Processing (ICPP), vol. 1, pp. 154-163, 1996.
27. J. Sahuquillo and A. Pont, "Splitting the Data Cache: A Survey," IEEE Concurrency, vol. 8, no. 3, pp. 30-35, July-Sept. 2000.
28. J.P. Shen and M.H. Lipasti, Modern Processor Design: Fundamentals of Superscalar Processors. Mcgraw-Hill, July 2004.
29. A.J. Smith, "Cache Memories," ACM Computing Surveys, vol. 14, no. 3, pp. 473-530, 1982.
30. Standard Performance Evaluation Corporation, SPEC2000 Benchmark Suite, http://www.spec.org, 2011.
31. R. Subramanian, Y. Smaragdakis, and G.H. Loh, "Adaptive Caches: Effective Shaping of Cache Behavior to Workloads," Proc. Ann. IEEE/ACM Int'l Symp. Microarchitecture, pp. 385-396, 2006. (Pubitemid 351337012)
32. D. Tarjan, S. Thoziyoor, and N.P. Jouppi, "CACTI 4.0," Technical Report HPL-2006-86, HP Laboratories, http://quid.hpl.hp. com:9081/cacti/, June 2006.
33. S.J. Walsh and J.A. Board, "Pollution Control Caching," Proc. Int'l Conf. Computer Design (ICCD), pp. 300-306, 1995.
34. N.H.E. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, third ed. Addison Wesley, 2005.