Power limitations and dark silicon challenge the future of multicore

ACM Transactions on Computer Systems

Volumn 30, Issue 3, 2012, Pages

  Esmaeilzadeh, Hadi ^a   Blem, Emily ^b   St Amant, Renée ^c   Sankaralingam, Karthikeyan ^b   DougBurger, Doug ^d  

^a UNIVERSITY OF WASHINGTON   (United States)

^b University of Wisconsin Madison   (United States)

^c University of Texas at Austin   (United States)

^d MICROSOFT RESEARCH   (United States)

Author keywords

Dark silicon; Modeling; Multicore; Power; Technology scaling

Indexed keywords

COMPUTING COMMUNITY; DEVICE-SCALING; MOORE'S LAW; MULTI CORE; MULTICORE CHIPS; MULTICORE DESIGN; PAPER MODELS; PARETO-OPTIMAL FRONTIERS; PERFORMANCE MODEL; POWER; POWER LIMITATIONS; PROCESSOR DESIGNERS; SCALING LIMITS; SINGLE-THREADED; TECHNOLOGY SCALING;

MODELS; TOPOLOGY;

PARALLEL PROCESSING SYSTEMS;

EID: 84866339572     PISSN: 07342071     EISSN: 15577333     Source Type: Journal    
DOI: 10.1145/2324876.2324879     Document Type: Article

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