An energy-efficient adaptive hybrid cache

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2011, Pages 67-72

  Cong, Jason ^a   Gururaj, Karthik ^a   Huang, Hui ^a   Liu, Chunyue ^a   Reinman, Glenn ^a   Zou, Yi ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Energy Reduction; Hybrid Cache; Scratchpad Memory

Indexed keywords

BALANCING TECHNIQUES; CACHE BEHAVIOR; CACHE SETS; DATA ARRAY; ENERGY EFFICIENT; ENERGY REDUCTION; HYBRID CACHE; MEMORY ACCESS PATTERNS; PRODUCTION REDUCTION; RUNTIMES; SCRATCH PAD MEMORY;

ENERGY EFFICIENCY; LOW POWER ELECTRONICS; POWER ELECTRONICS;

CACHE MEMORY;

EID: 80052721321     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISLPED.2011.5993609     Document Type: Conference Paper

References (27)

1. I. Issenin, E. Brockmeyer, M. Miranda, and N. Dutt, "DRDU: A data reuse analysis technique for efficient scratch-pad memory management," in ACM Trans. Des. Autom. Electron. Syst. vol. 12.2, p.15, 2007.
2. D. Chiou, P. Jain, L. Rudolph, and S. Devadas, "Application-specific memory management for embedded systems using software-controlled caches," in Proc. DAC, 2000, pp. 416-419.
3. C. Moritz, M. Frank, and S. Amarasinghe, "FlexCache: A framework for flexible compiler generated data caching," in Lecture Notes in Computer Science, vol. 2107, pp.135-146, 2001. (Pubitemid 33332790)
4. P. Ranganathan, S. Adve, and N. Jouppi, "Reconfigurable caches and their application to media processing," in Proc. ISCA, 2000, pp. 214-224.
5. H. Cook, K. Asanović, and D. Patterson, "Virtual local stores: Enabling software-managed memory hierarchies in mainstream computing environments," Technical Report No. UCB/EECS-2009-131, 2009.
6. J. Robertson and K. Gala, "Instruction and data cache locking on the e300 processor core," Freescale Application Note, 2006.
7. T. Kluter, P. Brisk, P. Ienne, and E. Charbon, "Way stealing: Cache-assisted automatic instruction set extensions," in Proc. DAC, 2009, pp. 31-36.
8. M. Qureshi, D. Thompson, and Y. Patt, "The V-way cache: Demand based associativity via global replacement," in Proc. ISCA, 2004, pp. 544-555. (Pubitemid 41548341)
9. E. G. Hallnor and S. K. Reinhardt, "A fully associative software-managed cache design," in Proc. ISCA, 2000, pp. 107-116.
10. D. Rolán, B. Fraguela, and R. Doallo, "Adaptive line placement with the set balancing cache," in Proc. MICRO, 2009, pp. 529-540.
11. N. Jouppi, "Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers," in Proc. ISCA, 1990, pp. 364-373.
12. C. Zhang, "Balanced cache: Reducing conflict misses of direct-mapped caches," in Proc. ISCA, 2006, pp. 155-166. (Pubitemid 46016612)
13. B. Agrawal and T. Sherwood. "Modeling TCAM power for next generation network devices," in Proc. ISPASS, 2006, pp.120-129. (Pubitemid 44711116)
14. M. Zhang and K. Asanovic, "Fine-grain CAM-tag cache resizing using miss tags," in Proc. ISLPED, 2002, pp.130-135.
15. A. Dominguez, S. Udayakumaran, and R. Barua, "Heap data allocation to scratch-pad memory in embedded systems," in J. Embedded Comput., vol. 1.4, pp. 521-540, 2005.
16. M. Verma, K. Petzold, L. Wehmeyer, H. Falk, and P. Marwedel, "Scratchpad sharing strategies for multiprocess embedded systems: A first approach," in Proc. ESTMEDIA, 2005, pp. 115-120. (Pubitemid 44250404)
17. J. Cong, H. Huang, C. Liu, and Y. Zou, "A reuse-aware prefetching algorithm for scratchpad memory," to appear in Proc. DAC, 2011.
18. LLVM compiler infrastructure: http://llvm.org/
19. T. Austin and G. Sohi, "Zero-cycle loads: microarchitecture support for reducing load latency," in Proc. MICRO, 1995, pp.82-92.
20. HP Cacti, http://quid.hpl.hp.com:9081/cacti/
21. C. Kun, S. Quan, and A. Mason, "A power-optimized 64-bit priority encoder utilizing parallel priority look-ahead," in Proc. ISCAS, 2004, pp. II 753-756.
22. P. Magnusson, M. Christensson, J. Eskilson, D. Forsgren, G. Hallberg, J. Hogberg, F. Larsson, A. Moestedt, and B. Werner, "Simics: A full system simulation platform," in IEEE Computer, vol. 35, pp. 50-58, 2002.
23. M. Martin, D. Sorin, B. Beckmann, M. Marty, M. Xu, A. Alameldeen, K. Moore, M. Hill, and D. Wood, "Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset," in Computer Architecture News, pp. 92-99, 2005.
24. M. Guthaus, J. Ringenberg, D. Ernst, T. Austin, T. Mudge, and R. Brown, "MiBench: A free, commercially representative embedded benchmark suite," in Workshop on Workload Characterization, 2001, pp. 3-14.
25. S. Bird, A. Phansalkar, L. K. John, A. Mericas, and R. Indukuru, "Performance characterization of SPEC CPU benchmarks on Intel's core microarchitecture based processor," in SPEC Benchmark Workshop, 2007.
26. www.cdsc.ucla.edu
27. S. Li, J. H. Ahn, R. Strong, J. Brockman, D. Tullsen, and N. Jouppi, "McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures," in Proc. MICRO, 2009, pp. 469-480.