Impact of cache architecture and interface on performance and area of FPGA-based processor/parallel-accelerator systems

Proceedings of the 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines, FCCM 2012

Volumn , Issue , 2012, Pages 17-24

  Choi, Jongsok ^a   Nam, Kevin ^a   Canis, Andrew ^a   Anderson, Jason ^a   Brown, Stephen ^a   Czajkowski, Tomasz ^b  

^a UNIVERSITY OF TORONTO   (Canada)

^b Altera Toronto Technology Centre   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION PERFORMANCE; ASSOCIATIVITY; BASELINE SYSTEMS; CACHE ARCHITECTURE; CACHE DESIGN; CACHE SIZE; CUSTOM HARDWARES; DDR2 SDRAM; HARDWARE ACCELERATORS; HARDWARE IMPLEMENTATIONS; MULTI-PUMPING; OFF-CHIP; PARALLEL ACCELERATORS; SEQUENTIAL SYSTEMS; SHARED MEMORY ARCHITECTURE; SOFT PROCESSORS; SYSTEM MODELS;

ACCELERATION; COMPUTERS; DESIGN; DYNAMIC RANDOM ACCESS STORAGE; HARDWARE; MEMORY ARCHITECTURE; MICROPROCESSOR CHIPS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 84864927000     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FCCM.2012.13     Document Type: Conference Paper

References (22)

1. M. Adler, K. Fleming, A. Parashar, M. Pellauer, and J. Emer. LEAP scratchpads: automatic memory and cache management for reconfigurable logic. In ACM Int'l Symp. on FPGAs, pages 25-28, 2011.
2. Altera, Corp., San Jose, CA. Nios II C2H Compiler User Guide, 2009.
3. Altera, Corp., San Jose, CA. Avalon Interface Specification, 2010.
4. Altera, Corp., San Jose, CA. SOPC Builder User Guide, 2010.
5. Altera, Corp., San Jose, CA. TriMatrix Embedded Memory Blocks in Stratix IV Devices, 2011.
6. S.-S. Ang, G. Constantinides, P. Cheung, and W. Luk. A flexible multiport caching scheme for reconfigurable platforms. In Applied Reconfigurable Computing, pages 205-216, 2006.
7. J. Bresenham. Algorithm for computer control of a digital plotter. IBM Systems Journal, 4, 1965.
8. A. Canis, J. Choi, M. Aldham, V. Zhang, A. Kammoona, J. Anderson, S. Brown, and T. Czajkowski. LegUp: High-level synthesis for FPGA-based processor/accelerator systems. In ACM Int'l Symp. on FPGAs, pages 33-36, 2011.
9. E. Chung, J. Hoe, and K. Mai. CoRAM: an in-fabric memory architecture for FPGA-based computing. In ACM Int'l Symnp. on FPGAs, pages 97-106, 2011.
10. J. Cong, K. Gururaj, Hui Huang, Chunyue Liu, G. Reinman, and Yi Zou. An energy-efficient adaptive hybrid cache. In IEEE Int'l Symp. on Low-Power Electronics and Design, pages 67-72, 2011.
11. J. Cong, W. Jiang, B. Liu, and Y. Zou. Automatic memory partitioning and scheduling for throughput and power optimization. ACM Trans. Des. Autom. Electron. Syst., 16, April 2011.
12. J. Cong and Y. Zou. FPGA-based hardware acceleration of lithographic aerial image simulation. ACM Trans. Reconfigurable Technol. Syst., 2(3):1-29, 2009.
13. DE4, Altera Corp, San Jose, CA. DE4 Development and Education Board, 2012.
14. C. Loken et al. SciNet: Lessons learned from building a power-efficient top-20 system and data centre. Journal of Physics: Conference Series, 256, 2010.
15. A. Gordon-Ross, F. Vahid, and N.D. Dutt. Fast configurable-cache tuning with a unified second-level cache. IEEE Trans. on VLSI, pages 80-91, 2009.
16. Y. Hara, H. Tomiyama, S. Honda, and H. Takada. Proposal and quantitative analysis of the CHStone benchmark program suite for practical C-based high-level synthesis. Journal of Information Processing, 17:242-254, 2009.
17. J. Hennessy and D. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kaufmann, 2006.
18. C.E. LaForest and J.G. Steffan. Efficient multi-ported memories for FPGAs. In ACM Int'l Symp. on FPGAs, pages 41-50, 2010.
19. A. Putnam, S. Eggers, D. Bennett, E. Dellinger, J. Mason, H. Styles, P. Sundararajan, and R. Wittig. Performance and power of cache-based reconfigurable computing. In Int'l Symp. on Computer Architecture, pages 395-405, 2009.
20. A. Santana Gil, J. Benavides Benitez, M. Hernandez Calvino, and E Herruzo Gomez. Reconfigurable cache implemented on an FPGA. In IEEE Int'l Conf. on Reconfigurable Computing, pages 250-255, 2010.
21. University of Cambridge. The Tiger "MIPS" processor (http://www.cl.cam.ac.uk/teaching/ 0910/ECAD+Arch/mips.html)., 2010.
22. P. Yiannacouras and J. Rose. A parameterized automatic cache generator for FPGAs. In IEEE Int'l Conf. on Field-Programmable Technology, pages 324-327, 2003.