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Volumn , Issue , 2010, Pages 41-50

Efficient multi-ported memories for FPGAs

Author keywords

FPGA; Memory; Multi port; Parallel

Indexed keywords

ARBITRARY NUMBER; AREA REDUCTION; BLOCK RAMS; CONVENTIONAL APPROACH; DESIGN SPACES; MEMORY LOCATIONS; MULTI-PORT; NEW DESIGN; OPERATING FREQUENCY; RANDOM ACCESS; SPEED IMPROVEMENT;

EID: 77951616343     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1723112.1723122     Document Type: Conference Paper
Times cited : (113)

References (17)
  • 1
    • 77951562344 scopus 로고    scopus 로고
    • July Application Note AC176, Accessed Sept. 2009
    • PLUS Devices. http://www.actel.com/documents/APA-MultiPort-AN.pdf, July 2003. Application Note AC176, Accessed Sept. 2009.
    • (2003) PLUS Devices
  • 2
  • 5
    • 77951604732 scopus 로고    scopus 로고
    • June Version 4.0, Accessed Sept. 2009
    • Nios II Performance Benchmarks. http://www.altera.com/literature/ds/ds- nios2-perf.pdf, June 2009. Version 4.0, Accessed Sept. 2009.
    • (2009) Nios II Performance Benchmarks
  • 6
    • 73549084404 scopus 로고    scopus 로고
    • March Version 9.0, Accessed Sept. 2009
    • Nios II Processor Reference Handbook. http://www.altera.com/literature/ hb/nios2/n2cpu-nii5v1.pdf, March 2009. Version 9.0, Accessed Sept. 2009.
    • (2009) Nios II Processor Reference Handbook
  • 16
    • 51549112659 scopus 로고    scopus 로고
    • September XAPP228 (v1.0), Accessed Sept. 2009
    • SAWYER, N., AND DEFOSSEZ, M. Quad-Port Memories in Virtex Devices. http://www.xilinx.com/support/documentation/application-notes/xapp228.pdf, September 2002. XAPP228 (v1.0), Accessed Sept. 2009.
    • (2002) Quad-Port Memories in Virtex Devices
    • Sawyer, N.1    Defossez, M.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.