Automatic memory partitioning and scheduling for throughput and power optimization

ACM Transactions on Design Automation of Electronic Systems

Volumn 16, Issue 2, 2011, Pages

  Cong, Jason ^a   Jiang, Wei ^a   Liu, Bin ^a   Zou, Yi ^a  

^a University of California   (United States)

Author keywords

Behavioral synthesis; Memory partition

Indexed keywords

ARRAY REFERENCES; BEHAVIORAL SYNTHESIS; COMPUTATION KERNEL; CYCLE ACCURATE; DYNAMIC POWER CONSUMPTION; ENERGY CONSUMPTION; HARD CONSTRAINTS; HARDWARE DESIGN; ILP FORMULATION; LARGE-SCALE PROBLEM; LIMITING FACTORS; LOOP PIPELINING; LOOP TILING; MEMORY ACCESS; MEMORY BANDWIDTHS; MEMORY BANKS; MEMORY BOTTLENECK; MEMORY PARTITION; MODERN EMBEDDED SYSTEMS; OPTIMIZED DESIGNS; PARTITION SCHEMES; PARTITIONING TECHNIQUES; POLYNOMIAL-TIME; POWER OPTIMIZATION; POWER REDUCTIONS; REAL-WORLD DESIGNS; RESOURCE SHARING; SCHEDULING INFORMATION; SCHEDULING PROBLEM; THROUGHPUT CONSTRAINTS; THROUGHPUT IMPROVEMENT;

CACHE MEMORY; EMBEDDED SOFTWARE; EMBEDDED SYSTEMS; ENERGY UTILIZATION; HEURISTIC ALGORITHMS; OPTIMIZATION; POLYNOMIAL APPROXIMATION; SYSTEMS ANALYSIS; THROUGHPUT;

DESIGN;

EID: 79953855900     PISSN: 10844309     EISSN: 15577309     Source Type: Journal    
DOI: 10.1145/1929943.1929947     Document Type: Article

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