Reconfigurable cache implemented on an FPGA

Proceedings - 2010 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2010

Volumn , Issue , 2010, Pages 250-255

  Santana Gil, A D ^a   Benavides Benitez, J I ^b   Hernandez Calvino M ^a   Herruzo Gomez E ^b  

^a UNIVERSITY OF HAVANA   (Cuba)

^b UNIVERSITY OF CÓRDOBA   (Spain)

Author keywords

Cache memory; FPGA; Reconfigurtion

Indexed keywords

ASSOCIATIVITY; CACHE PARAMETERS; CACHE SIZE; COMMON STRUCTURES; EMBEDDED PROCESSORS; FPGA; PERFORMANCE PARAMETERS; RE-CONFIGURABLE; RECONFIGURTION; TEST PLATFORMS; WORKING MODE;

ALGORITHMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); RECONFIGURABLE HARDWARE;

CACHE MEMORY;

EID: 79951791067     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ReConFig.2010.26     Document Type: Conference Paper

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