A parameterized automatic cache generator for FPGAs

Proceedings - 2003 IEEE International Conference on Field-Programmable Technology, FPT 2003

Volumn , Issue , 2003, Pages 324-327

  Yiannacouras, Peter ^a   Rose, Jonathan ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE GENERATOR; PARAMETERIZED; SOFT PROCESSORS; STORAGE COMPONENT; SYSTEM DESIGNERS; TARGET SYSTEMS; THREE PARAMETERS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 33751161188     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2003.1275768     Document Type: Conference Paper

References (5)

1. Altera Corporation. "Altera Stratix FPGA Family Data Sheet", December 2002. http://www.altera.com
2. Altera Corporation, "AN 119: Implementing High-Speed Search Applications with Altera CAM", in Altera Application Notes, July 2001. http://www.altera.com
3. J. L. Brelet. "Using Block RAM for High Performance Read/Write CAMs" in Xilinx Application Note xapp204. May 2000, http://www.xilinx.com
4. D. Lewis, V. Betz, D. Jefferson, A. Lee, C. Lane, P. Leventis, S. Marquardt, C. McClintock, B. Pedersen, G. Powell, S. Reddy, C. Wysocki, R. Cliff, and J. Rose, "The Stratix Routing and Logic Architecture" in FPGA'03, ACM. Symp. FPGAs, February 2003, pp. 15-20.
5. P. Yiannacouras, "An Automatic Cache Generator for Stratix FPGAs", BASc Thesis. University of Toronto, 2003. http://www.eecg.utoronto.ca/~yiannac/docs/bascthesis.pdf