Impact of error correction code and dynamic memory reconfiguration on high-reliability/low-cost server memory

IEEE International Integrated Reliability Workshop Final Report

Volumn , Issue , 2006, Pages 190-193

  Slayman, Charles ^a   Ma, Manny ^b   Lindley, Scott ^b  

^a SUN MICROSYSTEMS   (United States)

^b MICRON TECHNOLOGY INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC RANDOM ACCESS STORAGE; ERROR CORRECTION; FAILURE ANALYSIS; SERVERS;

DYNAMIC MEMORY RECONFIGURATION (DMR); ERROR CORRECTION CODES (ECC);

CODES (SYMBOLS);

EID: 41649118004     PISSN: 19308841     EISSN: 23748036     Source Type: Conference Proceeding    
DOI: 10.1109/IRWS.2006.305243     Document Type: Conference Paper

References (5)

1. C. L. Chen and M. Y. Hsiao, "Error-Correcting Codes for Semiconductor Memory Applications: A State-of-the-Art Review," IBM J. Res. Develop., vol. 28, no. 2, pp. 124-134, March 1984.
2. C. L. Chen, "Error-Correcting Codes for Byte-Organized Memory Systems," IEEE Trans. on Information Theory, vol. IT-32, no. 2, pp. 181-185, March 1986.
3. Timothy J. Dell, "A White Paper on the Benefits of Chipldll-Correct ECC for PC Server Main Memory," www.ibm.com/servers/eserver/pseries/ campaigns/chipkill.pdf
4. D. Tang, et al, "Assessment of the Effect of Memory Page Retirement on System RAS Against Hardware Faults," Int. Conf. on Dependable Sys. and Networks, pp. 16, June 2006.
5. "The IBM e server pSeries 690 - Reliability, Availability, Serviceability (RAS). A Technical Whitepaper," http://www-03.ibm.com/ servers/eserver/pseries/hardware/whitepapers/p690_ras2.html