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Volumn 30, Issue 3, 2010, Pages 34-47

Fine-grained activation for power reduction in DRAM

Author keywords

DRAM; DRAMsim; fine grained activation; low power design; memory system; posted CAS command

Indexed keywords

ADDITIONAL LOGIC; ARCHITECTURE OPTIMIZATION; DRAM DEVICES; LOW-POWER DESIGN; MEMORY CONTROLLER; MEMORY SYSTEMS; POWER CONSUMPTION; POWER REDUCTIONS;

EID: 77954599847     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2010.43     Document Type: Conference Paper
Times cited : (52)

References (11)
  • 2
    • 35348861182 scopus 로고    scopus 로고
    • DRAMsim: A Memory- System Simulator
    • D. Wang et al., ''DRAMsim: A Memory- System Simulator,'' ACM SIGARCH Computer Architecture News, vol.33, no.4, 2005, pp. 100-10
    • (2005) ACM SIGARCH Computer Architecture News , vol.33 , Issue.4 , pp. 100-107
    • Wang, D.1
  • 3
    • 77954610223 scopus 로고    scopus 로고
    • DDR2 SDRAM part no. MT47H256M4, data sheet
    • DDR2 SDRAM, part no. MT47H256M4, data sheet, Micron Technologies, 2004; http://download.micron.com/pdf/datasheets/ dram/ddr2/1GbDDR2.pdf.
    • (2004) Micron Technologies
  • 6
    • 77954581545 scopus 로고    scopus 로고
    • Calculating Memory System Power for DDR2,'' tech. note TN-47-104
    • ''Calculating Memory System Power for DDR2,'' tech. note TN-47-104, Micron Technologies, 2005; http://download.micron. com/pdf/technotes/ddr2/ tn4704.pdf.
    • (2005) Micron Technologies
  • 7
    • 77954594300 scopus 로고    scopus 로고
    • 128 M-Bit (4-Bank- 1 M-Word- 32-Bit) Single Data Rate I/F FCRAM, part no. MB81ES123245-10, data sheet DS05- 11440-2E
    • 128 M-Bit (4-Bank- 1 M-Word- 32-Bit) Single Data Rate I/F FCRAM, part no. MB81ES123245-10, data sheet DS05- 11440-2E, Fujitsu, 2006; http://www. datasheetdir.com/MB81ES123245-10+ download.
    • (2006) Fujitsu
  • 8
    • 0030395246 scopus 로고    scopus 로고
    • Scheduling for Minimizing the Number ofMemory Accesses in Low Power Applications
    • IEEE Press
    • R. Saied and C. Chakrabarti, ''Scheduling for Minimizing the Number ofMemory Accesses in Low Power Applications,'' Proc. Workshop VLSI Signal Processing, IEEE Press, 1996, pp. 169-178.
    • (1996) Proc. Workshop VLSI Signal Processing , pp. 169-178
    • Saied, R.1    Chakrabarti, C.2
  • 11
    • 0034856730 scopus 로고    scopus 로고
    • Concurrency, Latency, or System Overhead: Which Has the Largest Impact on Uniprocessor DRAM-System Performance?
    • ACM Press
    • V. Cuppu and B. Jacob, ''Concurrency, Latency, or System Overhead: Which Has the Largest Impact on Uniprocessor DRAM-System Performance?'' Proc. 28th Ann. Int'l Symp. Computer Architecture (ISCA 01), ACM Press, 2001, pp. 62-71.
    • (2001) Proc. 28th Ann. Int'l Symp. Computer Architecture (ISCA 01) , pp. 62-71
    • Cuppu, V.1    Jacob, B.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.