-
1
-
-
83455206178
-
Benefits and challenges of FDSOI technology for 14 nm node
-
Tempe, AZ
-
O. Faynot, "Benefits and challenges of FDSOI technology for 14 nm node," in Proc. IEEE Int. SOI, Tempe, AZ, 2011, pp. 1-21.
-
(2011)
Proc. IEEE Int. SOI
, pp. 1-21
-
-
Faynot, O.1
-
2
-
-
3943106832
-
Improved split C-V method for effective mobility extraction in sub-0.1-μm Si MOSFETs
-
Aug
-
K. Romanjek, F. Andrieu, T. Ernst, and G. Ghibaudo, "Improved split C-V method for effective mobility extraction in sub-0.1-μm Si MOSFETs," IEEE Electron Device Lett., vol. 25, no. 8, pp. 583-586, Aug. 2004.
-
(2004)
IEEE Electron Device Lett.
, vol.25
, Issue.8
, pp. 583-586
-
-
Romanjek, K.1
Andrieu, F.2
Ernst, T.3
Ghibaudo, G.4
-
3
-
-
0030785041
-
Quantitative mobility spectrum analysis of multicarrier conduction in semiconductors
-
J. R.Meyer, C. A. Hoffman, J. Antoszewski, and L. Faraone, "Quantitative mobility spectrum analysis of multicarrier conduction in semiconductors," J. Appl. Phys., vol. 81, no. 2, pp. 709-713, Jan. 1997. (Pubitemid 127667446)
-
(1997)
Journal of Applied Physics
, vol.81
, Issue.2
, pp. 709-713
-
-
Meyer, J.R.1
Hoffman, C.A.2
Antoszewski, J.3
Faraone, L.4
-
4
-
-
0031117193
-
Scaled silicon MOSFET's: Degradation of the total gate capacitance
-
PII S001893839702234X
-
D. Vasileska, D. K. Schroder, and D. K. Ferry, "Scaled silicon MOSFETs: Degradation of the total gate capacitance," IEEE Trans. Electron Devices, vol. 44, no. 4, pp. 584-587, Apr. 1997. (Pubitemid 127764562)
-
(1997)
IEEE Transactions on Electron Devices
, vol.44
, Issue.4
, pp. 584-587
-
-
Vasileska, D.1
Schroder, D.K.2
Ferry, D.K.3
-
5
-
-
0028747841
-
On the universality of inversion-layer mobility in Si MOSFETs: Part I. Effects of substrate impurity concentration
-
Dec
-
S. Takagi, S. Iwase, A. Toriumi, and H. Tango, "On the universality of inversion-layer mobility in Si MOSFETs: Part I. Effects of substrate impurity concentration," IEEE Trans. Electron Devices, vol. 41, no. 12, pp. 2357-2362, Dec. 1994.
-
(1994)
IEEE Trans. Electron Devices
, vol.41
, Issue.12
, pp. 2357-2362
-
-
Takagi, S.1
Iwase, S.2
Toriumi, A.3
Tango, H.4
-
6
-
-
0001114294
-
Electronic structures and phonon limited electron mobility of double-gate silicon-on-insulator Si inversion layers
-
Mar
-
M. Shoji and S. Horiguchi, "Electronic structures and phonon limited electron mobility of double-gate silicon-on-insulator Si inversion layers," J. Appl. Phys., vol. 85, no. 5, pp. 2722-2731, Mar. 1999.
-
(1999)
J. Appl. Phys.
, vol.85
, Issue.5
, pp. 2722-2731
-
-
Shoji, M.1
Horiguchi, S.2
-
7
-
-
33847337431
-
Front- and back-channel mobility in ultrathin SOI-MOSFETs by front-gate split CV method
-
DOI 10.1016/j.sse.2007.01.015, PII S0038110107000111
-
A. Ohata, M. Casse, and S. Cristoloveanu, "Front-and back-channel mobility in ultrathin SOI-MOSFETs by front-gate split CV method," Solid State Electron., vol. 51, no. 2, pp. 245-251, Feb. 2007. (Pubitemid 46330459)
-
(2007)
Solid-State Electronics
, vol.51
, Issue.2
, pp. 245-251
-
-
Ohata, A.1
Casse, M.2
Cristoloveanu, S.3
-
8
-
-
77952741736
-
Why the universal mobility is not
-
Jun
-
S. Cristoloveanu, N. Rodriguez, and F. Gamiz, "Why the universal mobility is not," IEEE Trans. Electron Devices, vol. 57, no. 6, pp. 1327-1333, Jun. 2010.
-
(2010)
IEEE Trans. Electron Devices
, vol.57
, Issue.6
, pp. 1327-1333
-
-
Cristoloveanu, S.1
Rodriguez, N.2
Gamiz, F.3
-
9
-
-
77957860766
-
Low leakage and low variability ultra-thin body and buried oxide (UT2B) SOI technology for 20 nm low power CMOS and beyond
-
San Francisco, CA
-
F. Andrieu, O. Weber, J. Mazurier, O. Thomas, J.-P. Noel, C. Fenouillet-Beranger, J.-P. Mazellier, P. Perreau, T. Poiroux, Y. Morand, T. Morel, S. Allegret, V. Loup, S. Barnola, F. Martin, J.-F. Damlencourt, I. M. Casse, X. G. Qne, O. Rozeau, M.-A. Jaud, G. Cibrario, J. Cluzel, A. Toffoli, F. Allain, R. Kies, D. Lafond, V. Delaye, C. Tabone, L. Tosti, L. Brevard, P. Gaud, V. Paruchuri, K. Bourdelle, W. Schwarzenbach, O. Bonnin, B.-Y. Nguyen, B. Doris, F. Buf, T. Skotnicki, and O. Faynot, "Low leakage and low variability ultra-thin body and buried oxide (UT2B) SOI technology for 20 nm low power CMOS and beyond," in Proc. Symp. VLSI Technol., San Francisco, CA, 2010, pp. 57-58.
-
(2010)
Proc. Symp. VLSI Technol.
, pp. 57-58
-
-
Andrieu, F.1
Weber, O.2
Mazurier, J.3
Thomas, O.4
Noel, J.-P.5
Fenouillet-Beranger, C.6
Mazellier, J.-P.7
Perreau, P.8
Poiroux, T.9
Morand, Y.10
Morel, T.11
Allegret, S.12
Loup, V.13
Barnola, S.14
Martin, F.15
Damlencourt, J.-F.16
Casse, I.M.17
Qne, X.G.18
Rozeau, O.19
Jaud, M.-A.20
Cibrario, G.21
Cluzel, J.22
Toffoli, A.23
Allain, F.24
Kies, R.25
Lafond, D.26
Delaye, V.27
Tabone, C.28
Tosti, L.29
Brevard, L.30
Gaud, P.31
Paruchuri, V.32
Bourdelle, K.33
Schwarzenbach, W.34
Bonnin, O.35
Nguyen, B.-Y.36
Doris, B.37
Buf, F.38
Skotnicki, T.39
Faynot, O.40
more..
-
10
-
-
67349140970
-
FDSOI devices with thin BOX and ground plane integration for 32 nm node and below
-
Jul
-
C. Fenouillet-Beranger, S. Denome, P. Perreau, C. Buj, O. Faynot, F. Andrieu, L. Tosti, S. Bamola, T. Salvetat, X. Garros, M. Casse, F. Allain, N. Ioubet, L. Pham-Ngyen, E. Deloffre, M. Gros-jean, R. Beneyton, C. Laviron, M. Marin, C. Leyris, S. Haendler, F. Leverd, P. Gouraud, P. Scheiblin, L. Clement, R. Pantel, S. Deleonibus, and T. Skotnicki, "FDSOI devices with thin BOX and ground plane integration for 32 nm node and below," Solid State Electron., vol. 53, no. 7, pp. 730-734, Jul. 2009.
-
(2009)
Solid State Electron.
, vol.53
, Issue.7
, pp. 730-734
-
-
Fenouillet-Beranger, C.1
Denome, S.2
Perreau, P.3
Buj, C.4
Faynot, O.5
Andrieu, F.6
Tosti, L.7
Bamola, S.8
Salvetat, T.9
Garros, X.10
Casse, M.11
Allain, F.12
Ioubet, N.13
Pham-Ngyen, L.14
Deloffre, E.15
Gros-Jean, M.16
Beneyton, R.17
Laviron, C.18
Marin, M.19
Leyris, C.20
Haendler, S.21
Leverd, F.22
Gouraud, P.23
Scheiblin, P.24
Clement, L.25
Pantel, R.26
Deleonibus, S.27
Skotnicki, T.28
more..
-
11
-
-
72049093481
-
In situ comparison of Si/High-κ and Si/SiO2 channel properties in SOI MOSFETs
-
Oct
-
L. Pham-Nguyen, C. Fenouillet-Berangerand, C. Vandooren, T. Skotnicki, G. Ghibaudo, and S. Cristoloveanu, "In situ comparison of Si/High-κ and Si/SiO2 channel properties in SOI MOSFETs.," IEEE Electron Device Lett., vol. 30, no. 10, pp. 1075-1077, Oct. 2009.
-
(2009)
IEEE Electron Device Lett.
, vol.30
, Issue.10
, pp. 1075-1077
-
-
Pham-Nguyen, L.1
Fenouillet-Berangerand, C.2
Vandooren, C.3
Skotnicki, T.4
Ghibaudo, G.5
Cristoloveanu, S.6
-
12
-
-
83455213673
-
Properties of 22 nm node extremely-thin-SOI MOSFETs
-
Tempe, AZ
-
N. Rodriguez, F. Andrieu, C. Navarro, O. Faynot, F. Gamiz, and S. Cristoloveanu, "Properties of 22 nm node extremely-thin-SOI MOSFETs," in Proc. IEEE Int. SOI, Tempe, AZ, 2011, pp. 1-2.
-
(2011)
Proc. IEEE Int. SOI
, pp. 1-2
-
-
Rodriguez, N.1
Andrieu, F.2
Navarro, C.3
Faynot, O.4
Gamiz, F.5
Cristoloveanu, S.6
|