Design and iso-area Vmin analysis of 9T subthreshold SRAM with bit-interleaving scheme in 65-nm CMOS

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 59, Issue 7, 2012, Pages 429-433

  Chang, Ming Hung ^a   Chiu, Yi Te ^a   Hwang, Wei ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Bit interleaving scheme; iso area analysis; subthreshold static random access memory (SRAM)

Indexed keywords

BUFFER STORAGE; CMOS INTEGRATED CIRCUITS; FEEDBACK; INTEGRATED CIRCUIT DESIGN; RADIATION HARDENING;

BIT-INTERLEAVING; ISO-AREA ANALYSIS; MINIMUM ENERGY POINT; OPERATION FREQUENCY; POSITIVE FEEDBACK LOOP; SOFT-ERROR TOLERANCE; STATIC RANDOM ACCESS MEMORY; SUB-THRESHOLD SRAM;

STATIC RANDOM ACCESS STORAGE;

EID: 84864116941     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2012.2198984     Document Type: Article

References (11)

1. B. H. Calhoun, J. F. Ryan, S. Khanna, M. Putic, and J. Lach, "Flexible circuits and architectures for ultralow power," Proc. IEEE, vol. 98, no. 2, pp. 267-282, Feb. 2010.
2. S. Hanson, B. Zhai, K. Bernstein, D. Blaauw, A. Bryant, L. Chang, K. K. Das, W. Haensch, E. J. Nowak, and D. M. Sylvester, "Ultralow-voltage, minimum-energy CMOS," IBM J. Res. Develop., vol. 50, no. 4/5, pp. 469-490, Jul./Sep. 2006.
3. H. Yamauchi, "A discussion on SRAM circuit design trend in deeper nanometer-scale technologies," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 5, pp. 763-774, May 2010.
4. N. Verma and A. P. Chandrakasan, "A 256 kb 65 nm 8T subthreshold SRAM employing sense-amplifier redundancy," IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 141-149, Jan. 2008.
5. T.-H. Kim, J. Liu, and C. H. Kim, "A voltage scalable 0.26V, 64 kb 8T SRAM with Vmin lowering techniques and deep sleep mode," IEEE J. Solid-State Circuits, vol. 44, no. 6, pp. 1785-1795, Jun. 2009.
6. P. Hazucha, T. Karnik, J. Maiz, S. Walstra, B. Bloechel, J. Tschanz, G. Dermer, S. Hareland, P. Armstrong, and S. Borkar, "Neutron soft error rate measurements in 90-nm CMOS process and scaling trends in SRAM from 0.25-μm to 90-nm generation," in IEDM Tech. Dig., Dec. 2003, pp. 21.5.1-21.5.4.
7. M. E. Sinangil, N. Verma, and A. P. Chandrakasan, "A 45nm 0.5V 8T column-interleaved SRAM with on-chip reference selection loop for sense-amplifier," in Proc. IEEE Asian Solid-State Circuits Conf., Nov. 2009, pp. 225-228.
8. I.J. Chang, J.-J. Kim, S. P. Park, and K. Roy, "A 32 kb 10T sub-threshold SRAM array with bit-interleaving and differential read scheme in 90 nm CMOS," IEEE J. Solid-State Circuits, vol. 44, no. 2, pp. 650-658, Feb. 2009.
9. A.-T. Do, J. Y. S. Low, J. Y. L. Low, Z.-H. Kong, X. Tan, and K.-S. Yeo, "An 8T differential SRAM with improved noise margin for bitinterleaving in 65 nm CMOS," IEEE Trans. Circuits Syst. I, vol. 58, no. 6, pp. 1252-1263, Jun. 2011.
10. M.-H. Chang, Y.-T. Chiu, S.-L. Lai, andW. Hwang, "A 1kb 9T subthreshold SRAM with bit-interleaving scheme in 65 nm CMOS," in Proc. Int. Symp. Low Power Electron. Des., Aug. 2011, pp. 291-296.
11. J. P. Kulkarni and K. Roy, "Ultralow-voltage process-variation- tolerant schmitt-trigger-based SRAM design," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 2, pp. 319-332, Feb. 2012.