A discussion on SRAM circuit design trend in deeper nanometer-scale technologies

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 18, Issue 5, 2010, Pages 763-774

  Yamauchi, Hiroyuki ^a  

^a FUKUOKA INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

Deeper nanometer scale; SRAM design solution; SRAM scaling; SRAM scaling trend

Indexed keywords

6T-SRAM; AREA OVERHEAD; AREA SCALING; CELL TERMINALS; CELL TOPOLOGY; CIRCUIT DESIGNS; DESIGN SOLUTIONS; EFFECTIVE OXIDE THICKNESS; MULTIPLE VOLTAGE; NANO-METER SCALE; NANOMETER-SCALE TECHNOLOGIES; POWER PROCESS; PROCESS NODES; RANDOM VARIATION; SCALING TRENDS; SEQUENCE CONTROL; SRAM DESIGN;

LOGIC DESIGN;

STATIC RANDOM ACCESS STORAGE;

EID: 77951880976     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2009.2016205     Document Type: Article

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