Methodology for analysis of TSV stress induced transistor variation and circuit performance

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn , Issue , 2012, Pages 216-222

  Yu, Li ^a   Chang, Wen Yao ^b   Zuo, Kewei ^b   Wang, Jean ^b   Yu, Douglas ^b   Boning, Duane ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; BIAXIAL STRESS; CIRCUIT PERFORMANCE; CMOS TECHNOLOGY; GEOMETRIC RELATIONS; GRID PARTITION; KEY CONSTRAINTS; LINEAR SUPERPOSITIONS; MECHANICAL STRESS; PATTERN OPTIMIZATION; POWER EFFICIENCY; RING OSCILLATOR; SILICON SURFACES; STRESS-INDUCED; TEST CASE; THERMAL MISMATCH; THRESHOLD VOLTAGE VARIATION; THROUGH SILICON VIAS; TRANSISTOR TYPES; TRANSISTOR VARIATION; VIABLE SOLUTIONS; WAFER FABRICATIONS;

ALGORITHMS; CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; FIELD EFFECT TRANSISTORS; FINITE ELEMENT METHOD; SILICON WAFERS; THREE DIMENSIONAL;

STRESSES;

EID: 84863685360     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2012.6187497     Document Type: Conference Paper

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