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Volumn , Issue , 2010, Pages 109-110

Impact of thinning and through silicon via proximity on high-k / metal gate first CMOS performance

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; ACTIVE DEVICES; BACK END STRUCTURES; CMOS SCALING; CMOS TECHNOLOGY; END-DEVICES; FRONT END; GATE FIRST; METAL GATE; MICRO RAMAN SPECTROSCOPY; MIXED-SIGNAL CIRCUITS; PERFORMANCE LIMITATIONS; RING OSCILLATOR; STRESS-INDUCED; THROUGH-SILICON-VIA; WAFER THINNING;

EID: 77957880771     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2010.5556190     Document Type: Conference Paper
Times cited : (20)

References (6)
  • 1
    • 77957881966 scopus 로고    scopus 로고
    • P. Morrow et al., MRSSP, 970, 2007;.
    • (2007) MRSSP , vol.970
    • Morrow, P.1
  • 2
    • 77952627377 scopus 로고    scopus 로고
    • Y.S. Kim et al. IEDM, 365-366, 2009;.
    • (2009) IEDM , pp. 365-366
    • Kim, Y.S.1
  • 3
    • 77953026885 scopus 로고    scopus 로고
    • G. Katti et al., IEDM, 357-358, 2009, .
    • (2009) IEDM , pp. 357-358
    • Katti, G.1
  • 4
    • 77957876073 scopus 로고    scopus 로고
    • C. Okoro et al., ECTC, 249-255, 2007.
    • (2007) ECTC , pp. 249-255
    • Okoro, C.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.