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Volumn , Issue , 2010, Pages 109-110
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Impact of thinning and through silicon via proximity on high-k / metal gate first CMOS performance
a a a a a a a a,b a,d a,d a a,d a a d a a a a a more.. |
Author keywords
[No Author keywords available]
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Indexed keywords
3-D INTEGRATION;
ACTIVE DEVICES;
BACK END STRUCTURES;
CMOS SCALING;
CMOS TECHNOLOGY;
END-DEVICES;
FRONT END;
GATE FIRST;
METAL GATE;
MICRO RAMAN SPECTROSCOPY;
MIXED-SIGNAL CIRCUITS;
PERFORMANCE LIMITATIONS;
RING OSCILLATOR;
STRESS-INDUCED;
THROUGH-SILICON-VIA;
WAFER THINNING;
CMOS INTEGRATED CIRCUITS;
ELECTRIC SIGNAL SYSTEMS;
INTEGRATED CIRCUITS;
RAMAN SPECTROSCOPY;
SEMICONDUCTING SILICON COMPOUNDS;
SILICON WAFERS;
VLSI CIRCUITS;
OSCILLATORS (ELECTRONIC);
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EID: 77957880771
PISSN: 07431562
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/VLSIT.2010.5556190 Document Type: Conference Paper |
Times cited : (20)
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References (6)
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