Bandwidth-aware reconfigurable cache design with hybrid memory technologies

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2011, Pages 48-55

  Zhao, Jishen ^a   Xu, Cong ^a   Xie, Yuan ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH DEMAND; BANDWIDTH-AWARE; CACHE DESIGN; CACHE HIERARCHIES; CHIP-MULTIPROCESSOR; EMBEDDED DRAM; HYBRID MEMORIES; LIMITED MEMORY; MEMORY TECHNOLOGY; MULTITHREADED; ON CHIP MEMORY; PERFORMANCE GAIN; PREDICTION ENGINES; RE-CONFIGURABLE; RECONFIGURATION MECHANISMS; STATISTICAL PREDICTION; SYSTEM THROUGHPUT;

BANDWIDTH; COMPUTER AIDED DESIGN; DYNAMIC RANDOM ACCESS STORAGE; MULTIPROGRAMMING; STATIC RANDOM ACCESS STORAGE; TECHNOLOGY;

CACHE MEMORY;

EID: 84862971010     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2011.6105304     Document Type: Conference Paper

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