Fortuitous detection and its impact on test set sizes using stuck-at and transition faults

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn 2002-January, Issue , 2002, Pages 177-185

  Dworak, J ^a   Wingfield, J ^a   Cobb, B ^a   Lee, Sooryong ^a   Wang, L C ^b   Mercer, M R ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

^b University of California   (United States)

Author keywords

Benchmark testing; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Fault diagnosis; Manufacturing; System testing; Test pattern generators; Timing

Indexed keywords

DEFECTS; DESIGN FOR TESTABILITY; ELECTRIC FAULT LOCATION; FAILURE ANALYSIS; FAULT TOLERANCE; MANUFACTURE; TIMING CIRCUITS; VLSI CIRCUITS;

BENCHMARK TESTING; CIRCUIT FAULTS; CIRCUIT TESTING; ELECTRICAL FAULT DETECTIONS; SYSTEM TESTING; TEST PATTERN GENERATOR; TIMING;

FAULT DETECTION;

EID: 84862384708     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFTVS.2002.1173514     Document Type: Conference Paper

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