On the use of fault dominance in n-detection test generation

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2001, Pages 352-357

  Pomeranz, I ^a   Reddy, S M ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TESTING; COMBINATORIAL CIRCUITS; COMPUTER SIMULATION; FAILURE ANALYSIS; GATES (TRANSISTOR);

AUTOMATIC TEST PATTERN GENERATION; DETECTION TEST GENERATION; FAULT DOMINANCE;

INTEGRATED CIRCUIT TESTING;

EID: 0035015861     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

1. An experimental chip to evaluate test techniques experiment results
2. Compact test sets for high defect coverage
3. Analysis of pattern-dependent and timing-dependent failures in an experimental test chip
4. REDO - Random excitation and deterministic observation - First commercial experiment
5. Test sequences to achieve high defect coverage for synchronous sequential circuits
6. On n-detection test sets and variable n-detection test sets for transition faults
7. Quantifying non-target defect detection by target fault test sets
8. On the decline of testing efficiency as the fault coverage approaches 100%
9. A CMOS fault extractor for inductive fault analysis
10. Defect-based tests: A key enabler for successful migration to structural test