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Volumn , Issue , 2003, Pages 544-550

Binding, allocation and floorplanning in low power high-level synthesis

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER AIDED SOFTWARE ENGINEERING; GRAPH THEORY; MATHEMATICAL MODELS; OPTIMIZATION;

EID: 0346778589     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iccad.2003.159736     Document Type: Conference Paper
Times cited : (41)

References (17)
  • 1
    • 0030645043 scopus 로고    scopus 로고
    • A roadmap of CAD tool changes for sub-micron interconnect problems
    • L. Scheffer, "A roadmap of CAD tool changes for sub-micron interconnect problems", in International Symosium on Physical Design, 1997.
    • (1997) International Symosium on Physical Design
    • Scheffer, L.1
  • 5
    • 0030206111 scopus 로고    scopus 로고
    • Low-power architectural synthesis and the impact of exploiting locality
    • R. Mehra, L. M. Guerra, and J. M. Rabaey, "Low-power architectural synthesis and the impact of exploiting locality", in J. VLSI Signal Processing, 1996.
    • (1996) J. VLSI Signal Processing
    • Mehra, R.1    Guerra, L.M.2    Rabaey, J.M.3
  • 6
    • 35248862850 scopus 로고    scopus 로고
    • SCALP: An iterative-improvement-based low power data path synthesis system
    • A. Raghunathan, and N. K. Jha, "SCALP: An iterative-improvement-based low power data path synthesis system", in Proc. Int. Conf. Computer-Aided Design, 1997.
    • (1997) Proc. Int. Conf. Computer-aided Design
    • Raghunathan, A.1    Jha, N.K.2
  • 9
    • 0031651853 scopus 로고    scopus 로고
    • Simultaneous scheduling, binding and floorplanning in high-level synthesis
    • P. Prabhakaran, and P. Banerjee: "Simultaneous scheduling, binding and floorplanning in high-level synthesis", in Proc. Int. Conf. VLSI Design, 1998.
    • (1998) Proc. Int. Conf. VLSI Design
    • Prabhakaran, P.1    Banerjee, P.2
  • 10
    • 0036911919 scopus 로고    scopus 로고
    • Interconnect-aware High-level Synthesis for Low Power
    • L. Zhong, and N.K. Jha "Interconnect-aware High-level Synthesis for Low Power", in ICCAD, 2002.
    • (2002) ICCAD
    • Zhong, L.1    Jha, N.K.2
  • 17
    • 0346237857 scopus 로고    scopus 로고
    • Digital Integrated Circuits
    • J. M. Rabaey "Digital Integrated Circuits", in Prentice Hall, 1996.
    • (1996) Prentice Hall
    • Rabaey, J.M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.