Ultra low power litho friendly local assist circuitry for variability resilient 8T SRAM

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2012, Pages 1042-1047

  Sharma, Vibhu ^a,b   Cosemans, Stefan ^a,c   Ashouei, Maryam ^b   Huisken, Jos ^b   Catthoor, Francky ^a,c   Dehaene, Wim ^a,c  

^a UNIVERSITY OF LEUVEN   (Belgium)

^b HOLST CENTRE   (Netherlands)

^c IMEC   (Belgium)

Author keywords

litho optimized; local write receiver; SRAM 8T cell; variation; Write Margin

Indexed keywords

COST REDUCTION; ENERGY UTILIZATION; LITHOGRAPHY; STATIC RANDOM ACCESS STORAGE; T-CELLS; TIMING CIRCUITS;

8T-CELL; CIRCUIT TECHNIQUES; LITHO OPTIMIZED; READ ACCESS TIME; STATE OF THE ART; STATISTICAL SIMULATION; VARIATION; WRITE MARGIN;

LOW POWER ELECTRONICS;

EID: 84862078473     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2012.6176649     Document Type: Conference Paper

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