Port interference faults in two-port memories

IEEE International Test Conference (TC)

Volumn , Issue , 1999, Pages 1001-1010

  Hamdioui, Said ^a   van de Goor, A J ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DATA STORAGE EQUIPMENT; EMBEDDED SYSTEMS; INTERFACES (COMPUTER); MATHEMATICAL MODELS; RANDOM ACCESS STORAGE;

FAULT COVERAGE; LOGICAL FAULT MODELS; MARCH TEST; MULTIPORT MEMORIES; PORT INTERFERENCE FAULTS;

FAULT TOLERANT COMPUTER SYSTEMS;

EID: 0033325501     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)