-
1
-
-
0142210226
-
High-precision TDC in an FPGA using a 192 MHz quadrature clock
-
Nov. 10-16
-
M. D. Fries and J. J.Williams, "High-precision TDC in an FPGA using a 192 MHz quadrature clock," in Proc. IEEE Nucl. Sci. Symp., Nov. 10-16, 2002, vol. 1, pp. 580-584.
-
(2002)
Proc. IEEE Nucl. Sci. Symp.
, vol.1
, pp. 580-584
-
-
Fries, M.D.1
Williams, J.J.2
-
2
-
-
11844296685
-
Firmware-only implementation of time-to-digital converter (TDC) in field programmable gate array (FPGA)
-
Oct. 19-25
-
J. Wu, Z. Shi, and I. Y. Wang, "Firmware-only implementation of time-to-digital converter (TDC) in field programmable gate array (FPGA)," in Proc. IEEE Nucl. Sci. Symp., Oct. 19-25, 2003, vol. 1, pp. 177-181.
-
(2003)
Proc. IEEE Nucl. Sci. Symp.
, vol.1
, pp. 177-181
-
-
Wu, J.1
Shi, Z.2
Wang, I.Y.3
-
3
-
-
33846607677
-
An FPGA-based, 12-channel TDC and digital signal processing module for the RatCAP scanner
-
Oct. 23-29
-
S. S. Junnarkar et al., "An FPGA-based, 12-channel TDC and digital signal processing module for the RatCAP scanner," in Proc. IEEE Nucl. Sci. Symp., Oct. 23-29, 2005, vol. 2, pp. 919-923.
-
(2005)
Proc. IEEE Nucl. Sci. Symp.
, vol.2
, pp. 919-923
-
-
Junnarkar, S.S.1
-
4
-
-
33645714885
-
A high-resolution time-to-digital converter implemented in field-programmable-gate-arrays
-
Feb.
-
J. Song, Q. An, and S. Liu, "A high-resolution time-to-digital converter implemented in field-programmable-gate-arrays," IEEE Trans. Nucl. Sci, vol. 53, no. 1, pp. 236-241, Feb. 2006.
-
(2006)
IEEE Trans. Nucl. Sci
, vol.53
, Issue.1
, pp. 236-241
-
-
Song, J.1
An, Q.2
Liu, S.3
-
5
-
-
34547582110
-
FPGA-based high area efficient time-to-digital IP design
-
Nov.
-
M. Lin, G. Tsai, C. Liu, and S. Chu, "FPGA-based high area efficient time-to-digital IP design," in Proc. IEEE Region 10 Conf., Nov. 2006, pp. 1-4.
-
(2006)
Proc. IEEE Region 10 Conf.
, pp. 1-4
-
-
Lin, M.1
Tsai, G.2
Liu, C.3
Chu, S.4
-
6
-
-
34548836832
-
On the timing uncertainty in delay-line-based time measurement applications targeting FPGAs
-
May
-
A. Amiri, A. Khouas, and M. Boukadoum, "On the timing uncertainty in delay-line-based time measurement applications targeting FPGAs," in Proc. IEEE Int. Symp. Circuits Syst., May 2007, pp. 3772-3775.
-
(2007)
Proc. IEEE Int. Symp. Circuits Syst.
, pp. 3772-3775
-
-
Amiri, A.1
Khouas, A.2
Boukadoum, M.3
-
7
-
-
67649206459
-
The 10-ps wave union TDC: Improving FPGA TDC resolution beyond its cell delay
-
Oct. 19-25
-
J.Wu and Z. Shi, "The 10-ps wave union TDC: Improving FPGA TDC resolution beyond its cell delay," in Proc. IEEE Nucl. Sci. Symp., Oct. 19-25, 2008, pp. 3440-3446.
-
(2008)
Proc. IEEE Nucl. Sci. Symp.
, pp. 3440-3446
-
-
Wu, J.1
Shi, Z.2
-
8
-
-
67650692189
-
A 17 ps time-to-digital converter implemented in 65 nm FPGA technology
-
C. Favi and E. Charbon, "A 17 ps time-to-digital converter implemented in 65 nm FPGA technology," in Proc. FPGA'09, 2009, pp. 113-120.
-
(2009)
Proc. FPGA'09
, pp. 113-120
-
-
Favi, C.1
Charbon, E.2
-
9
-
-
71549138823
-
Double sampling architecture for performing fine time interpolation with a limited logic density FPGA
-
S. Liu, J.Wang, K. Chen, and Q. An, "Double sampling architecture for performing fine time interpolation with a limited logic density FPGA," in Proc. 9th Int. Conf. Electron. Meas. Instrum., 2009, pp. 1-585.
-
(2009)
Proc. 9th Int. Conf. Electron. Meas. Instrum.
, pp. 1-585
-
-
Liu, S.1
Wang, J.2
Chen, K.3
An, Q.4
-
10
-
-
72749104623
-
On-chip processing for the wave union TDC implemented in FPGA
-
May 10-15
-
J. Wu, "On-chip processing for the wave union TDC implemented in FPGA," in Proc. IEEE-NPSS Real Time Conf., May 10-15, 2009, pp. 279-282.
-
(2009)
Proc. IEEE-NPSS Real Time Conf.
, pp. 279-282
-
-
Wu, J.1
-
11
-
-
77951153345
-
An FPGA wave union TDC for time-of-Flight applications
-
Oct. 25-31
-
J.Wu, "An FPGA wave union TDC for time-of-Flight applications," in Proc. IEEE Nucl. Sci. Symp. Conf. Rec, Oct. 25-31, 2009, pp. 299-304.
-
(2009)
Proc. IEEE Nucl. Sci. Symp. Conf. Rec
, pp. 299-304
-
-
Wu, J.1
-
13
-
-
77951170305
-
A fully fledged TDC implemented in field-programmable gate arrays
-
Apr.
-
J. Wang, S. Liu, Q. Shen, H. Li, and Q. An, "A fully fledged TDC implemented in field-programmable gate arrays," IEEE Trans. Nucl. Sci, vol. 57, no. 2, pp. 446-450, Apr. 2010.
-
(2010)
IEEE Trans. Nucl. Sci
, vol.57
, Issue.2
, pp. 446-450
-
-
Wang, J.1
Liu, S.2
Shen, Q.3
Li, H.4
An, Q.5
-
14
-
-
84971462198
-
A high precision time-to-digital converter based on multi-phase clock implemented within field-programmablegate- array
-
K. Chen, S. Liu, and Q. An, "A high precision time-to-digital converter based on multi-phase clock implemented within field-programmablegate- array," Nucl. Sci. Techniques, vol. 21, pp. 123-128, 2010.
-
(2010)
Nucl. Sci. Techniques
, vol.21
, pp. 123-128
-
-
Chen, K.1
Liu, S.2
An, Q.3
-
15
-
-
77953691785
-
Several key issues on implementing delay line based TDCs using FPGAs
-
Jun.
-
J. Wu, "Several key issues on implementing delay line based TDCs using FPGAs," IEEE Trans. Nucl. Sci, vol. 57, no. 3, pp. 1543-1548, Jun. 2010.
-
(2010)
IEEE Trans. Nucl. Sci
, vol.57
, Issue.3
, pp. 1543-1548
-
-
Wu, J.1
-
16
-
-
78349239378
-
A novel 10 ps resolution TDC architecture implemented in a 130 nm process FPGA
-
M. Daigneault and J. David, "A novel 10 ps resolution TDC architecture implemented in a 130 nm process FPGA," in Proc. 8th IEEE Int. NEWCAS Conf., 2010, pp. 281-284.
-
(2010)
Proc. 8th IEEE Int. NEWCAS Conf.
, pp. 281-284
-
-
Daigneault, M.1
David, J.2
-
17
-
-
0028444571
-
Effect of additive dither on the resolution of ideal quantizers
-
Mar.
-
P. Carbone and D. Petri, "Effect of additive dither on the resolution of ideal quantizers," IEEE Trans. Instrum. Meas., vol. 43, no. 3, pp. 389-396, Mar. 1994.
-
(1994)
IEEE Trans. Instrum. Meas.
, vol.43
, Issue.3
, pp. 389-396
-
-
Carbone, P.1
Petri, D.2
-
18
-
-
84860408099
-
-
The MathWorks, Inc. Version 7.6.0.324
-
The MathWorks, Inc. Version 7.6.0.324.
-
-
-
-
19
-
-
84860397719
-
-
DG645 Digital Delay Generator User Manual, Stanford Research Systems, Revision 1.1
-
DG645 Digital Delay Generator User Manual, Stanford Research Systems, Revision 1.1.
-
-
-
-
20
-
-
0021586344
-
Full-speed testing of A/D converters
-
Dec.
-
J. Doernberg, H.-S. Lee, and D. A. Hodges, "Full-speed testing of A/D converters," IEEE J. Solid-State Circuits, vol. SSC-19, no. 6, pp. 820-827, Dec. 1984.
-
(1984)
IEEE J. Solid-State Circuits
, vol.SSC-19
, Issue.6
, pp. 820-827
-
-
Doernberg, J.1
Lee, H.-S.2
Hodges, D.A.3
-
21
-
-
1642619421
-
Review of methods for time interval measurements with picosecond resolution
-
J. Kalisz, "Review of methods for time interval measurements with picosecond resolution," Metrologis, vol. 41, pp. 17-32, 2004.
-
(2004)
Metrologis
, vol.41
, pp. 17-32
-
-
Kalisz, J.1
-
22
-
-
84971378435
-
LUT-based non-linearity compensation for BES III TOF's time measurement
-
S. Liu, C. Feng, H. Yan, and Q. An, "LUT-based non-linearity compensation for BES III TOF's time measurement," Nucl. Sci. Techniques, vol. 21, pp. 49-53, 2010.
-
(2010)
Nucl. Sci. Techniques
, vol.21
, pp. 49-53
-
-
Liu, S.1
Feng, C.2
Yan, H.3
An, Q.4
-
23
-
-
36749113053
-
Standard deviation of averaged time interval measurements
-
G. A. Reider, "Standard deviation of averaged time interval measurements," Rev. Sci. Instrum, vol. 51, no. 10, pp. 1423-1424, 1980.
-
(1980)
Rev. Sci. Instrum
, vol.51
, Issue.10
, pp. 1423-1424
-
-
Reider, G.A.1
|