On the timing uncertainty in delay-line-based time measurement applications targeting FPGAs

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2007, Pages 3772-3775

  Amiri, Amir M ^a   Khouas, Abdelhakim ^a   Boukadoum, Mounir ^b  

^a ÉCOLE POLYTECHNIQUE DE MONTRÉAL   (Canada)

^b UNIVERSITÉ DU QUÉBEC À MONTRÉAL   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

OPTIMIZATION; OSCILLATORS (ELECTRONIC); TIME DELAY; UNCERTAINTY ANALYSIS;

CELL DELAYS; INTRA-DIE DELAY MISMATCHES; TDC CIRCUITS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 34548836832     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iscas.2007.378782     Document Type: Conference Paper

References (6)

1. Amir M. Amiri, et Al., "Low Dead Time, Multi-hit, FPGA-based Time-to-Dgital Converter"; proc. IEEE NEWCAS 2006, Gatineau (Canada), June 2006, pp. 29-32.
2. kalisz, J et Al, "Field-Programmable-Gate-Array-Based Time-to-Digital Converter with 200-ps Resolution"; IEEE Trans. on Instrumentation and Measurement, 46-1, pp.51-55, 1997.
3. Jinyuan Wu, et al.; "Firmware-only Implementation of Time-to-Digital Converter (TDC) in Field-Programmable Gate Array (FPGA)"; Nuclear Science Symp. Conference Record, 2003 IEEE Volume 1, 19-25 Oct. 2003 Page(s):177-181
4. Antonio H. Chan, et Al, "A Jitter Characterization System Using a Component-Invariant Vernier Delay Line", IEEE Transactions On (VLSI) Systems, VOL. 12, NO. 1, Jan, 2004.
5. Nassif, S. R.; "Modeling and analysis of manufacturing variations"; IEEE Conference on Custom Integrated Circuits, 6-9 May 2001 Page(s):223-228
6. B. Zhou, A. Khouas, "Measurement of delay mismatch due to process variations by means of modified ring oscillators", IEEE International Symposium on Circuits and Systems, 2005, Vol.5, pp. 5246-5249