A high-resolution time-to-digital converter implemented in field-programmable-gate-arrays

IEEE Transactions on Nuclear Science

Volumn 53, Issue 1, 2006, Pages 236-241

  Song, Jian ^a   An, Qi ^a   Liu, Shubin ^a  

^a UNIVERSITY OF SCIENCE AND TECHNOLOGY OF CHINA   (China)

Author keywords

Code density test; Field programmable gate arrays (FPGAs); Time measurement; Time to digital converter (TDC)

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CALIBRATION; CODES (SYMBOLS); INTERPOLATION; TIME MEASUREMENT;

CODE DENSITY TEST; FIRST-IN FIRST-OUT (FIFO) BUFFER; TIME-TO-DIGITAL CONVERTER (TDC);

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 33645714885     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2006.869820     Document Type: Article

References (38)

1. B. K. Swann, B. J. Blalock, L. G. Clonts, D. M. Binkley, J. M. Rochelle, E. Breeding, and K. M. Baldwin, "A 100 ps time-resolution CMOS time-to-digital converter for positron emission tomography imaging applications," IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1839-1852, Nov. 2004.
2. K. Karadamoglou, N. P. Paschalidis, E. Sarris, N. Stamatopoulos, G. Kottaras, and V. Paschalidis, "An 11-bit high-resolution and adjustable-range CMOS time-to-digital converter for space science instruments," IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 214-222, Jan. 2004.
3. K. Maatta and J. Kostamovaara, "A high-precision time-to-digital converter for pulsed time-of-flight laser radar applications," IEEE Trans. Instrum. Meas., vol. 47, no. 2, pp. 521-536, Apr. 1998.
4. H. Matsumoto, O. Sasaki, K. Anraku, and M. Nozaki, "Low power high resolution TDC with fast data conversion for balloon-borne experiments," IEEE Trans. Nucl. Sci., vol. 43, pp. 2195-2198, Aug. 1996.
5. F. Bigongiari, R. Roncella, R. Saletti, and P. Terreni, "A 250-ps time resolution CMOS multihit time-to-digital converter for nuclear physics experiments," IEEE Trans. Nucl. Sci., vol. 46, no. 4, pp. 73-77, Apr. 1999.
6. S. Minutoli and E. Robutti, "A 96-channel, 500 ps resolution TDC board for the BaBar experiment at SLAC," IEEE Trans. Nucl. Sci., vol. 47, no. 2, pp. 147-150, Apr. 2000.
7. R. Arcidiacono et al., "A new drift chamber TDC readout for the high intensity program of the NA48 experiment," Nucl. Instum. Methods, vol. A518, pp. 493-494, Feb. 2004.
8. "Preliminary design report of BEPCII-BESIII detector," in Institute, of High Energy Physics of Chinese Academy of Sciences: BESIII International Collaboration, 2004, pp. 99-145.
9. J. Kalisz, "Review of methods for time interval measurements with picosecond resolution," Metrologis, vol. 41, pp. 17-32, 2004.
10. Q. An, Review of methods and techniques of precise time interval measurements for high energy physics experiments, in Nuclear Techniques. to be published.
11. "Dept. Elect. Eng. Comput.," Ph.D. dissertation, Tech. Univ. Lisbon, Lisbon, Portugal, Oct. 2000.
12. M. Mota and J. Christiansen, "A high-resolution time interpolator based on a delay locked loop and an R-C delay line," IEEE J. Solid-State Circuits, vol. 34, no. 10, pp. 1360-1366, Oct. 1999.
13. J. Christiansen, "High performance time-to-digital converter (version 2.2)," in CERN Digital Microelectronics Group, Mar. 2004. CERN.
14. P. Dudek, S. Szczepanski, and J. V. Hatfield, "A high-resolution CMOS time-to-digital converter utilizing a vernier delay line," IEEE Trans. Solid-State Circuits, vol. 35, no. 2, pp. 240-247, Feb. 2000.
15. J. Kalisz, R. Szplet, and A. Poniecki, "Field programmable gate array based time-to-digital converter with 200-ps resolution," IEEE Trans. Instrum. Meas., vol. 46, no. 1, pp. 51-55, Feb. 1997.
16. R. Szplet, J. Kalisz, and R. Szymanowski, "Interpolating time counter with 100 ps resolution on a single FPGA device," IEEE Trans. Instrum. Meas., vol. 49, no. 4, pp. 879-883, Aug. 2000.
17. M. S. Andaloussi, M. Boukadoum, and E.-M. Aboulhamid, "A novel time-to-digital converter with 150 ps time resolution and 2.5 ns pulsepair resolution," in 14th Int. Conf. Microelectron., 2002, pp. 123-126.
18. M. D. Fries and J. J. Williams, "High-precision TDC in an FPGA using a 192-MHz quadrature clock," in Proc. IEEE Conf. Rec. NSS., vol. 1, 2002, pp. 580-584.
19. J. Wu, Z. Shi, and I. Y. Wang, "Firmware-only implementation of time-to-digital converter in field programmable gate array," in Proc. IEEE Conf. Rec. NSS., vol. 1, 2003, pp. 177-181.
20. M. Zielinski, D. Chaberski, M. Kowalski, R. Frankowski, and S. Grzelak, "High-resolution time-interval measuring system implemented in single FPGA device," Measurement, vol. 35, pp. 311-317, 2004.
21. D. K. Xie, Q. C. Zhang, G. S. Qi, and D. Y. Xu, "Cascading delay line time-to-digital converter with 75 ps resolution and a reduced number of delay cells," Rev. Sci. Instrum., vol. 76, 2005. 014701.
22. R. Szymanowski and J. Kalisz, "Field programmable gate array time counter with two-stage interpolation," Rev. Sci. Instrum., vol. 76, 2005. 045104.
23. H. Chen, Q. An, P. Zhang, and Y. Wang, "High precision short time-interval measurement system," Nucl. Elect. Dele. Technol., vol. 19, pp. 51-54, Jan. 1999.
24. J. Liu and Q. An, "Analysis of the factors that influence the time resolution of TOF in BESIII detector," High Energy Phys. Nucl. Phys., vol. 28, pp. 1170-1175, Nov. 2004.
25. J. Song, Q. An, S. Liu, C. Ye, N. Zhang, and J. Li, "Design of precision time measure system based on virtual instrumentation," in Proc. Laser Interactional Matter, 2005, pp. 1-5.
26. W. Shen, S. Liu, J. Liu, and Q. An, "Research on a high precision synchronous time stretcher in BESIII," J. Univ. Sci. Technol. China, vol. 35, Dec. 2005.
27. J. Song, Q. An, and S. Liu, "High-precision time interval measure instrument based on PCI," J. Elect. Meas. Instrum., vol. 20, Jun. 2006.
28. S. Liu, J. Song, and Q. An, "Test of data driven TDC application in high energy physics experiments," in Nucl. Techniques, unpublished.
29. J. U. Horstmann, H. W. Eichel, and R. L. Coates, "Metastability behavior of CMOS ASIC flip-flops in theory and test," IEEE J. Solid- State Circuits, vol. 24, no. 2, pp. 146-157, Feb. 1989.
30. C. Foley, "Characterizing metastability," in Proc. 2nd IEEE Symp. Adv. Res. Asynchronous Circuits Syst., vol. 18-21, 1996, pp. 175-184.
31. R. Szymanowski, "Metastability effects in a two-stage time interpolator," Metrology Meas. Syst., vol. x, pp. 319-329, 2003.
32. T. H. Cormen, C. E. Leiserson, R. L. Rivest, and C. Stein, Introduction to Algorithms, 2nd ed. New York: McGraw-Hill, 2001, pt. 12.
33. C. Ljuslin, J. Christiansen, A. Marchioro, and O. Klingsheim, "An integrated 16-channel CMOS time to digital converter," IEEE Trans. Nucl. Sci., vol. 41, no. 4, pp. 1104-1108, Aug. 1994.
34. ACEX 1 K Programmable. Logic Device Family Data Sheet. San Jose, CA: Altera Corp., May 2003.
35. Virtex-II Platform FPGAs: complete Data Sheet. San Jose, CA: Xilinx Inc., Jun. 2004.
36. J. Doernberg, H.-S. Lee, and D. A. Hodges, "Full-speed testing of A/D converters," IEEE J. Solid-State Circuits, vol. SSC-19, no. 6, pp. 820-827, Dec. 1984.
37. A. Mantyniemi, T. Rahkonen, and J. Kostamovaara, "A nonlinearity-corrected CMOS time digitizer IC with 20 ps single-shot precision," in Proce. IEEE Int. Symp. Circuits Syst., 2002, pp. I-513-I-516.
38. J. Kalisz, M. Pawlowski, and R. Pelka, "A simple, precise, and low jitter delay/gate generator," Rev. Sci. Instrum., vol. 74, pp. 3507-3509, 2003.