FPGA-based high area efficient time-to-digital IP design

IEEE Region 10 Annual International Conference, Proceedings/TENCON

Volumn , Issue , 2006, Pages

  Lin, Min Chuan ^a   Tsai, Guo Ruey ^a   Liu, Chun Yi ^a   Chu, Shi Shien ^a  

^a KUN SHAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); LOGIC GATES; NETWORK ROUTING; OPTICAL RESOLVING POWER; OSCILLATORS (ELECTRONIC); PRODUCT DESIGN;

INTELLIGENT PROPERTY; RING OSCILLATORS; TIME TO DIGITAL CONVERTERS;

INTELLIGENT AGENTS;

EID: 34547582110     PISSN: 21593442     EISSN: 21593450     Source Type: Conference Proceeding    
DOI: 10.1109/TENCON.2006.343706     Document Type: Conference Paper

References (8)

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7. A. H. Chan, G. W. Roberts (2004), "A Jitter Characterization System Using a Component-Invariant Vernier Delay Line", IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Vol. 12, No. 1, pp79-95, JANUARY, 2004.
8. Min-Chuan Lin and Guo-Ruey Tsai, (2005), NSC93-2215-E-168-004 Project Report, National Science Council, Taiwan, ROC.