Performance of Partial Reconfiguration in FPGA systems: A survey and a cost model

ACM Transactions on Reconfigurable Technology and Systems

Volumn 4, Issue 4, 2011, Pages

  Papadimitriou, Kyprianos ^a   Dollas, Apostolos ^a   Hauck, Scott ^b  

^a TECHNICAL UNIVERSITY OF CRETE   (Greece)

^b UNIVERSITY OF WASHINGTON   (United States)

Author keywords

Field programmable gate arrays; Partial reconfiguration; Reconfigurable computing; Reconfiguration time

Indexed keywords

BITSTREAMS; CONFIGURATION BITSTREAM; COST MODELS; DESIGN FLOWS; EXISTING SYSTEMS; ORDERS OF MAGNITUDE; PARTIAL RECONFIGURATION; PERCENTAGE ERROR; PHYSICAL COMPONENTS; REAL MEASUREMENTS; REALISTIC MODEL; RECONFIGURABLE COMPUTING; RECONFIGURABLE DEVICES; RECONFIGURATION PROCESS; RECONFIGURATION TIME; SYSTEM ARCHITECTURES;

RECONFIGURABLE ARCHITECTURES; RECONFIGURABLE HARDWARE; SURVEYS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 84859467647     PISSN: 19367406     EISSN: 19367414     Source Type: Journal    
DOI: 10.1145/2068716.2068722     Document Type: Article

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