A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration

Proceedings - 21st International Parallel and Distributed Processing Symposium, IPDPS 2007; Abstracts and CD-ROM

Volumn , Issue , 2007, Pages

  Claus, Christopher ^a   Müller, Florian H ^a   Zeppenfeld, Johannes ^a   Stechele, Walter ^a  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

Author keywords

Dynamic partial self reconfiguration; ICAP; Reconfiguration time

Indexed keywords

INTERFACES (COMPUTER); MICROPROCESSOR CHIPS; PARALLEL PROCESSING SYSTEMS; PROGRAM PROCESSORS; STORAGE ALLOCATION (COMPUTER);

DYNAMIC PARTIAL RECONFIGURATION (DPR); INTERNAL CONFIGURATION ACCESS PORTS (ICAP); PROCESSOR LOCAL BUS (PLB); RUN TIME RECONFIGURATION;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 34548757272     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2007.370362     Document Type: Conference Paper

References (17)

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