Run-time partial reconfiguration speed investigation and architectural design space exploration

FPL 09: 19th International Conference on Field Programmable Logic and Applications

Volumn , Issue , 2009, Pages 498-502

  Liu, Ming ^a,b   Kuehn, Wolfgang ^a   Lu, Zhonghai ^b   Jantsch, Axel ^b  

^a JUSTUS LIEBIG UNIVERSITY   (Germany)

^b ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

BIT STREAM; BLOCK RAMS; DESIGN ARCHITECTURE; DIRECT MEMORY ACCESS; FPGA FABRIC; INTERNAL CONFIGURATION ACCESS PORTS; IP CORE; ORDER OF MAGNITUDE; PARTIAL RECONFIGURATION; RECONFIGURATION TIME; RESOURCE CONSUMPTION; RUNTIMES; SPEED LIMIT; XPS;

ARCHITECTURAL DESIGN; RANDOM ACCESS STORAGE; SPACE RESEARCH;

COMPUTER CRIME;

EID: 70449922693     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2009.5272463     Document Type: Conference Paper

References (14)

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