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Volumn , Issue , 2008, Pages 535-538

A multi-platform controller allowing for maximum dynamic partial reconfiguration throughput

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMOBILE DRIVERS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); SPEED; THROUGHPUT;

EID: 54949092869     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2008.4630002     Document Type: Conference Paper
Times cited : (79)

References (12)
  • 1
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    • Autovision - A Run-time Reconfigurable MPSoC Architecture for Future Driver Assistance Systems
    • Mar
    • C. Claus, W. Stechele, and A. Herkersdorf, "Autovision - A Run-time Reconfigurable MPSoC Architecture for Future Driver Assistance Systems," Information Technology, vol. 49, no. 3, pp. 181-186, Mar. 2007.
    • (2007) Information Technology , vol.49 , Issue.3 , pp. 181-186
    • Claus, C.1    Stechele, W.2    Herkersdorf, A.3
  • 3
    • 37549048144 scopus 로고    scopus 로고
    • V. Tadigotla and L. S. ans Sesh Commuri, FPGA Implementation of Dynamic Run-Time Behavior Reconfiguration in Robots, in Proceedings of ISIC '06, Munich, Germany, Oct. 2006, pp. 1220-1225.
    • V. Tadigotla and L. S. ans Sesh Commuri, "FPGA Implementation of Dynamic Run-Time Behavior Reconfiguration in Robots," in Proceedings of ISIC '06, Munich, Germany, Oct. 2006, pp. 1220-1225.
  • 4
    • 54949091060 scopus 로고    scopus 로고
    • A Self-Reconfigurable Computing Platform Hardware Architecture
    • cs.AR/0411075, Nov
    • A. Weisensee and D. Nathan, "A Self-Reconfigurable Computing Platform Hardware Architecture," CoRR, vol. cs.AR/0411075, no. 8, pp. 1-5, Nov. 2004.
    • (2004) CoRR, vol , Issue.8 , pp. 1-5
    • Weisensee, A.1    Nathan, D.2
  • 5
    • 47349093324 scopus 로고    scopus 로고
    • Complexity and Performance Evaluation of Two Partial Reconfiguration Interfaces on FPGAs: A Case Study
    • Las Vegas, Nevada, USA, June
    • H. Tan, R. F. DeMara, A. J. Thakkar, A. Ejnioui, and J. Sattler, "Complexity and Performance Evaluation of Two Partial Reconfiguration Interfaces on FPGAs: A Case Study," in Proceedings of ERSA'06, Las Vegas, Nevada, USA, June 2006, pp. 253-256.
    • (2006) Proceedings of ERSA'06 , pp. 253-256
    • Tan, H.1    DeMara, R.F.2    Thakkar, A.J.3    Ejnioui, A.4    Sattler, J.5
  • 6
    • 34548757272 scopus 로고    scopus 로고
    • A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration,
    • Long Beach, California, USA, Mar
    • C. Claus, F. H. Müller, J. Zeppenfeld, and W. Stechele, "A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration, " in Proceedings IPDPS'07, Long Beach, California, USA, Mar. 2007, pp. 1-7.
    • (2007) Proceedings IPDPS'07 , pp. 1-7
    • Claus, C.1    Müller, F.H.2    Zeppenfeld, J.3    Stechele, W.4
  • 7
    • 54949110461 scopus 로고    scopus 로고
    • J. Zeppenfeld, LIS-IPIF Specification, Lehrstuhl für Integrierte Systeme, Arcisstraβe 21, D-80290 München, 2006, www.lis.ei.tum.de/?lisipif.
    • J. Zeppenfeld, "LIS-IPIF Specification", Lehrstuhl für Integrierte Systeme, Arcisstraβe 21, D-80290 München, 2006, www.lis.ei.tum.de/?lisipif.
  • 8
    • 54949143879 scopus 로고    scopus 로고
    • Virtex-II Pro and Virtex-II Pro X FPGA User Guide (UG012), v4.0 ed., Xilinx Inc., 2100 Logic Drive, San Jose CA 95124, Mar. 2005.
    • "Virtex-II Pro and Virtex-II Pro X FPGA User Guide (UG012)", v4.0 ed., Xilinx Inc., 2100 Logic Drive, San Jose CA 95124, Mar. 2005.
  • 9
    • 54949099883 scopus 로고    scopus 로고
    • Virtex-4 Configuration Guide, vl.9 ed., Xilinx Inc., 2100 Logic Drive, San Jose CA 95124, Oct. 2007.
    • "Virtex-4 Configuration Guide", vl.9 ed., Xilinx Inc., 2100 Logic Drive, San Jose CA 95124, Oct. 2007.
  • 10
    • 54949109261 scopus 로고    scopus 로고
    • OPB HWICAP Product Specification, Xilinx Inc., 2100 Logic Drive, San Jose CA 95124, Mar. 2005.
    • "OPB HWICAP Product Specification", Xilinx Inc., 2100 Logic Drive, San Jose CA 95124, Mar. 2005.
  • 11
    • 54949104252 scopus 로고    scopus 로고
    • Xilinx University Program Virtex-II Pro Development System Hardware Reference Manual, vl.0 ed., Xilinx Inc., 2100 Logic Drive, San Jose CA 95124, Mar. 2005.
    • "Xilinx University Program Virtex-II Pro Development System Hardware Reference Manual", vl.0 ed., Xilinx Inc., 2100 Logic Drive, San Jose CA 95124, Mar. 2005.
  • 12
    • 54949089120 scopus 로고    scopus 로고
    • ML410 Embedded Development Platform User Guide, vl.7 ed., Xilinx Inc., 2100 Logic Drive, San Jose CA 95124, Sept. 2007.
    • "ML410 Embedded Development Platform User Guide", vl.7 ed., Xilinx Inc., 2100 Logic Drive, San Jose CA 95124, Sept. 2007.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.