Pick-and-place silver sintering die attach of small-area chips

IEEE Transactions on Components, Packaging and Manufacturing Technology

Volumn 2, Issue 2, 2012, Pages 199-207

  Kähler, Julian ^a   Heuck, Nicolas ^a   Stranz, Andrej ^a   Waag, Andreas ^a   Peiner, Erwin ^a  

^a TECHNICAL UNIVERSITY OF BRAUNSCHWEIG   (Germany)

Author keywords

Nanoparticles; semiconductor device packaging; silver sintering

Indexed keywords

BONDING PROCESS; FINITE ELEMENT MODELING; FLIP-CHIP BONDERS; HARSH ENVIRONMENT; LOW TEMPERATURES; MEASUREMENT WHILE DRILLINGS; NANO SILVER; OPERATION RANGE; PICK-AND-PLACE; PLACEMENT ACCURACY; SEMICONDUCTOR DEVICE PACKAGING; SERIES PRODUCTION; SILVER LAYER; SURFACE DAMAGES;

ADHESION; ELECTRONICS INDUSTRY; ELECTRONICS PACKAGING; NANOPARTICLES; SINTERING; SURFACE PROPERTIES; WELL DRILLING;

SILVER;

EID: 84859089703     PISSN: 21563950     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCPMT.2011.2170571     Document Type: Article

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