SoC HW/SW verification and validation

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2011, Pages 297-300

  Huang, Chung Yang ^a   Yin, Yu Fan ^a   Hsu, Chih Jen ^a   Huang, Thomas B ^b   Chang, Ting Mao ^b  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^b InPA Systems Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ABSTRACTION LEVEL; COSIMULATION; DESIGN FLOWS; DIFFERENT MODES; FPGA PROTOTYPING; KEY COMPONENT; PRODUCT QUALITY; PROTOTYPING; SIMULATION SPEED; SOC DESIGNS; SYSTEMC; TIME-TO-MARKET; VERIFICATION AND VALIDATION; VIRTUAL PROTOTYPING;

COMPUTER AIDED DESIGN; COMPUTER SOFTWARE;

LOGIC DESIGN;

EID: 79952936054     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2011.5722202     Document Type: Conference Paper

References (8)

1. Cadence, http://www.cadence.com
2. Mentor Graphics, http://www.mentor.com/
3. EVE, http://www.eve-team.com/
4. Synopsys, http//www.synopsys.com
5. The Dini Group, http://www.dinigroup.com
6. S2C, http://www.S2Cinc.com/
7. InPA Systems, "InPA Co-emulator User Manual", 2009.
8. Accellera, "Standard Co-Emulation Modeling Interface (SCE-MI) Reference Manual", 2007.