FPGA prototyping of a multi-million gate system-on-chip (SoC) design for wireless USB applications

Proceedings of the 2009 ACM International Wireless Communications and Mobile Computing, Connecting the World Wirelessly, IWCMC 2009

Volumn , Issue , 2009, Pages 1355-1358

  Subramanian, P ^a   Patil, Jagonda ^a   Saxena, Manish Kumar ^a  

^a Samsung Electronics India Software Operations Ltd   (India)

Author keywords

ASIC (application specific integrated circuits); Clock gating; ECMA 368; FPGA; FPGA physical implementation; FPGA synthesis; Functional verification; Soc (System on chip); Synthesis constraints

Indexed keywords

APPLICATION PROGRAMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTEGRATED CIRCUIT DESIGN; PROGRAMMABLE LOGIC CONTROLLERS; SOFTWARE DESIGN; TIMING CIRCUITS;

APPLICATION SPECIFIC INTEGRATED CIRCUIT; APPLICATION-SPECIFIC INTEGRATED CIRCUITS; ARRAY SYNTHESIS; CLOCK-GATINGS; ECMA-368; FIELD PROGRAMMABLE GATE ARRAY; FIELD PROGRAMMABLE GATE ARRAY-PHYSICAL IMPLEMENTATION; FIELD PROGRAMMABLE GATE ARRAY-SYNTHESIS; FIELD PROGRAMMABLES; FUNCTIONAL VERIFICATION; PROGRAMMABLE GATE ARRAY; SYNTHESIS CONSTRAINT; SYSTEM-ON-CHIP; SYSTEMS-ON-CHIP;

SYSTEM-ON-CHIP;

EID: 70450265364     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1582379.1582676     Document Type: Conference Paper

References (6)

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