Rapid design and analysis of communication systems using the BEE hardware emulation environment

Proceedings of the International Workshop on Rapid System Prototyping

Volumn 2003-January, Issue , 2003, Pages 148-154

  Chang, Chen ^a   Kuusilinna, K ^b   Richards, B ^a   Chen, A ^a   Chan, N ^a   Brodersen, R W ^a   Nikolic B ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

Author keywords

Application specific integrated circuits; Clocks; Digital signal processing; Emulation; Engines; Field programmable gate arrays; Hardware; Prototypes; Signal design; Software design

Indexed keywords

APPLICATION PROGRAMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; CLOCKS; COMPUTER HARDWARE; COMPUTER SOFTWARE; DATA FLOW GRAPHS; DIGITAL INTEGRATED CIRCUITS; DIGITAL SIGNAL PROCESSING; ENGINES; EQUIVALENT CIRCUITS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; RAPID PROTOTYPING; SIGNAL PROCESSING; SOFTWARE PROTOTYPING;

DIGITAL SIGNAL PROCESSING (DSP); EMULATION; HARDWARE AND SOFTWARE; INTEGRATED RAPID PROTOTYPING; PROCESSING CAPABILITY; PROTOTYPES; REAL-TIME RAPID PROTOTYPING; SIGNAL DESIGN;

SOFTWARE DESIGN;

EID: 84941286621     PISSN: 10746005     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IWRSP.2003.1207042     Document Type: Conference Paper

References (7)

1. C. Chang, K. Kuusilinna, B. Richards, and R.W. Brodersen, "Implementation of BEE: a Real-time Large-scale Hardware Emulation Engine," Proc. FPGA 2003, pp. 91-99, Feb. 2003.
2. K. Kuusilinna, C. Chang, M.J. Ammer, B. Richards, and R.W. Brodersen, "Designing BEE: a Hardware Emulation Engine for Signal Processing in Low-Power Wireless Applications," EURASIP Journal on Applied Signal Processing, special issue on Rapid Prototyping of DSP Systems, 2003.
3. A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, Low Power CMOS Digital Design, Kluwer, 1995.
4. http://www.synopsys.com/products/datapath/datapath.html.
5. L. Bahl, J. Cocke, F. Jelinek, and R. Raviv, "Optimal Decoding of Linear Codes for Minimizing Symbol Error Rate," IEEE Trans. Information Theory, vol. 20, no. 2, pp. 284-287, Mar. 1974.
6. E. Yeo, P. Pakzad, B. Nikoliô, and V. Anantharam, "VLSI architectures for iterative decoders in magnetic recording channels," IEEE Trans. Magnetics, vol. 37, no. 2, pp. 748-755, Mar. 2001.
7. B. Shackleford, M.Tanaka, R.J. Carter, and G. Snide, "FPGA Implementation of Neighborhood-of-Four Cellular Automata Random Number Generators," Proc. FPGA 2002, pp. 106-112, Feb. 2002.