DEEP: An iterative FPGA-based many-core emulation system for chip verification and architecture research

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 2011, Pages 115-118

  Ributzka, Juergen ^a   Hayashi, Yuhei ^a   Gao, Guang R ^a   Chen, Fei ^b  

^a UNIVERSITY OF DELAWARE   (United States)

^b ARM Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURAL FEATURES; ARCHITECTURE RESEARCH; CHIP ARCHITECTURE; CO-VERIFICATION; DEBUGGING SUPPORT; DELAWARES; EMULATION PLATFORM; EMULATION SYSTEM; HARDWARE DESIGN AND VERIFICATION; HARDWARE/SOFTWARE; MANY-CORE; MANY-CORE ARCHITECTURE;

LOGIC DESIGN; LOGIC GATES; PROGRAM PROCESSORS; VERIFICATION;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 79952972128     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1950413.1950438     Document Type: Conference Paper

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