Advanced channel engineering achieving aggressive reduction of V T variation for ultra-low-power applications

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2011, Pages

  Fujita, K ^a   Torii, Y ^a   Hori, M ^a   Oh, J ^a   Shifren, L ^c   Ranade, P ^c   Nakagawa, M ^b   Okabe, K ^a   Miyake, T ^a   Ohkoshi, K ^a   Kuramae, M ^a   Mori, T ^a   Tsuruta, T ^b   Thompson, S ^c   Ema, T ^a  

^a Fujitsu Semiconductor Ltd   (Japan)

^b Suvolta Inc ^*  (Japan)

^c SuVolta Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

T-CELLS; TEMPERATURE;

AGGRESSIVE REDUCTION; BULK MOSFET; CHANNEL ENGINEERING; CHANNEL FORMATION; LOW TEMPERATURE PROCESSING; SRAM STATIC NOISE MARGIN; ULTRALOW POWER APPLICATION; VT VARIATION;

ELECTRON DEVICES;

EID: 84857010260     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2011.6131657     Document Type: Conference Paper

References (9)

1. A. J. Bhavnagarwala et al., "A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing," IEEE J. Solid-State Circuits, vol. 43, pp. 946-955, 2008
2. A. Asenov et al., "Simulation of Intrinsic Parameter Fluctuations in Decananometer and Nanometer-Scale MOSFETs," IEEE Trans. Electron Devices, vol. 50, pp. 1837-1852, 2003
3. A. Asenov et al., "Intrinsic Parameter Fluctuations in Decananometer MOSFETs Introduced by Gate Line Edge Roughness," IEEE Trans. Electron Devices, vol. 50, pp. 1254-1260, 2003
4. A. R. Brown, G. Roy and A. Asenov, "Poly-Si-Gate-Related Variability in Decananometer MOSFETs With Conventional Architecture," IEEE Trans. Electron Devices, vol. 54, pp. 3056-3063, 2007 (Pubitemid 350123890)
5. Q. Liu, et al., "Impact of Back Bias on Ultra-Thin Body and BOX (UTBB) Devices," Symp. VLSI Tech., pp.160-161, 2011
6. K. J. Kuhn, "CMOS Scaling for 22nm Node and Beyond: Device Physics and Technology," 2011 International Symposium on VLSI Technology., Systems and Application (VLSI-TSA), Date:25-27 April 2011
7. A. Asenov, and S. Saini, "Suppression of Random Dopant-Induced Threshold Voltage Fluctuations in Sub-0.1-&μυ;m MOSFET's with Epitaxial and δ-Doped Channels," IEEE Trans. Electron Devices, vol. 46, pp. 1718-1724, 1999
8. K. Noda et al., "A 0.1-&μυ;m Delta-Doped MOSFET Fabricated with Post-Low-Energy Implanting Selective Epitaxy," IEEE Trans. Electron Devices, vol. 45, pp. 809-814, 1998
9. A. Hokazono et al., "25-nm Gate Length nMOSFET With Steep Channel Profiles Utilizing Carbon-Doped Silicon Layers," IEEE Trans. Electron Devices, vol. 58, pp. 1302-1310, 2011