메뉴 건너뛰기




Volumn 58, Issue 5, 2011, Pages 1302-1310

25-nm gate length nMOSFET with steep channel profiles utilizing carbon-doped silicon layers (A P-type dopant confinement layer)

Author keywords

Carbon doped Si (Si:C); epitaxial layers (epi layer); mobility; random dopant fluctuation; steep channel profile

Indexed keywords

A-CARBON; CHANNEL PROFILE; CHANNEL STRUCTURES; DIFFUSIVITIES; DOPED SILICON; GATE LENGTH; MOBILITY; MOSFETS; N-CHANNEL; NMOSFET; NMOSFETS; P-TYPE; P-TYPE DOPANT; RANDOM DOPANT FLUCTUATION; SI LAYER; STEEP CHANNEL PROFILE;

EID: 79955525576     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2011.2112770     Document Type: Article
Times cited : (8)

References (15)
  • 1
    • 0026896303 scopus 로고
    • Scaling the Si MOSFET: From bulk to SOI to bulk
    • Jul
    • R.-H. Yan, A. Ourmazd, and K. F. Lee, "Scaling the Si MOSFET: From bulk to SOI to bulk," IEEE Trans. Electron Devices, vol. 39, no. 7, pp. 1704-1710, Jul. 1992.
    • (1992) IEEE Trans. Electron Devices , vol.39 , Issue.7 , pp. 1704-1710
    • Yan, R.-H.1    Ourmazd, A.2    Lee, K.F.3
  • 4
    • 0000115765 scopus 로고    scopus 로고
    • A 0.1-μ m delta-doped MOSFET fabricated with post-low-energy implanting selective epitaxy
    • Apr
    • K. Noda, T. Tatsumi, T. Uchida, K. Nakajima, H. Miyamoto, and C Hu, "A 0.1-μ m delta-doped MOSFET fabricated with post-low-energy implanting selective epitaxy," IEEE Trans. Electron Devices, vol. 45, no. 4, pp. 809-814, Apr. 1998.
    • (1998) IEEE Trans. Electron Devices , vol.45 , Issue.4 , pp. 809-814
    • Noda, K.1    Tatsumi, T.2    Uchida, T.3    Nakajima, K.4    Miyamoto, H.5    Hu, C.6
  • 5
    • 0031237178 scopus 로고    scopus 로고
    • Suppression of oxidation-enhanced boron diffusion in silicon by carbon implantation and characterization of mosfet's with carbon-implanted channels
    • PII S0018938397061327
    • I. Ban, M. C Ozturk, and E. K. Demirlioglu, "Suppression of oxidation-enhanced boron diffusion in silicon by carbon implanta-tion and characterization of MOSFETs with carbon-implanted chan-nels," IEEE Trans. Electron Devices, vol. 44, no. 9, pp. 1544-1551, Sep. 1997. (Pubitemid 127764678)
    • (1997) IEEE Transactions on Electron Devices , vol.44 , Issue.9 , pp. 1544-1551
    • Ban, I.1    Ozturk, M.C.2    Demirlioglu, E.K.3
  • 10
    • 77952326043 scopus 로고    scopus 로고
    • Steep channel profiles in n/pMOS controlled by boron-doped Si:C layers for continual bulk-CMOS scaling
    • A. Hokazono, H. Itokawa, I. Mizushima, S. Kawanaka, S. Inaba, and Y. Toyoshima, "Steep channel profiles in n/pMOS controlled by boron-doped Si:C layers for continual bulk-CMOS scaling," in IEDM Tech. Dig., 2009, pp. 673-676.
    • (2009) IEDM Tech. Dig , pp. 673-676
    • Hokazono, A.1    Itokawa, H.2    Mizushima, I.3    Kawanaka, S.4    Inaba, S.5    Toyoshima, Y.6
  • 12
    • 58049132814 scopus 로고    scopus 로고
    • TCAD analysis for channel profile engineer-ing with carbon doped Si(Si:C) layer for post-32 nm node bulk planar nMOSFETs
    • N. Kusunoki, A. Hokazono, S. Kawanaka, I. Mizushima, H. Yoshimura, M. Iwai, and F Matsuoka, "TCAD analysis for channel profile engineer-ing with carbon doped Si(Si:C) layer for post-32 nm node bulk planar nMOSFETs," in Proc ESSDERC, 2008, pp. 178-181.
    • (2008) Proc ESSDERC , pp. 178-181
    • Kusunoki, N.1    Hokazono, A.2    Kawanaka, S.3    Mizushima, I.4    Yoshimura, H.5    Iwai, M.6    Matsuoka, F.7
  • 13
    • 0033689413 scopus 로고    scopus 로고
    • Optimum conditions of body effect factor and substrate bias in variable threshold vol-tage MOSFETs
    • Apr
    • H. Koura, M. Takamiya, and T. Hiramoto, "Optimum conditions of body effect factor and substrate bias in variable threshold vol-tage MOSFETs," Jpn. J. Appl. Phys., vol. 39, no. 4B, pp. 2312-2317, Apr. 2000.
    • (2000) Jpn. J. Appl. Phys. , vol.39 , Issue.4 B , pp. 2312-2317
    • Koura, H.1    Takamiya, M.2    Hiramoto, T.3
  • 14
    • 39749173824 scopus 로고    scopus 로고
    • Beneath-the-channel strain-transfer-structure (STS) and em-bedded source/drain stressors for strain and performance enhancement of nanoscale MOSFETs
    • K.-W. Ang, J. Lin, C.-H. Tung, N. Balasubramanian, G. Samudra, and Y.-C. Yeo, "Beneath-the-channel strain-transfer-structure (STS) and em-bedded source/drain stressors for strain and performance enhancement of nanoscale MOSFETs," in VLSISymp. Tech. Dig., 2007, pp. 42-43.
    • (2007) VLSISymp. Tech. Dig , pp. 42-43
    • Ang, K.-W.1    Lin, J.2    Tung, C.-H.3    Balasubramanian, N.4    Samudra, G.5    Yeo, Y.-C.6
  • 15
    • 0029306018 scopus 로고
    • Channel profile engineering for MOSFETs with 100 nm channel lengths
    • May
    • J. B. Jacobs and D. Antoniadis, "Channel profile engineering for MOSFETs with 100 nm channel lengths," IEEE Trans. Electron Devices, vol. 42, no. 5, pp. 870-875, May 1995.
    • (1995) IEEE Trans. Electron Devices , vol.42 , Issue.5 , pp. 870-875
    • Jacobs, J.B.1    Antoniadis, D.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.