CPACT - The conditional parameter adjustment cache tuner for dual-core architectures

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2011, Pages 396-403

  Rawlins, Marisha ^a   Gordon Ross, Ann ^a,b  

^a J Crayton Pruitt Family Department of Biomedical Engineering   (United States)

^b NSF Center for High Performance Reconfigurable Computing   (United States)

Author keywords

cache tuning; embedded systems; energy savings; low power; multi core

Indexed keywords

AVERAGE ENERGY; CACHE CONFIGURATIONS; CACHE TUNING; DATA CACHES; DATA COHERENCE; DESIGN SPACES; DUAL-CORE; LOW POWER; MULTI CORE; MULTICORE ARCHITECTURES; MULTITHREADED; OPTIMAL CONFIGURATIONS; SUBSTANTIAL ENERGY;

COMPUTER ARCHITECTURE; DESIGN; EMBEDDED SYSTEMS; ENERGY CONSERVATION;

CACHE MEMORY;

EID: 83455219851     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2011.6081429     Document Type: Conference Paper

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