Fast configurable-cache tuning with a unified second-level cache

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2005, Pages 323-326

  Gordon Ross, Ann ^a   Vahid, Frank ^a,b   Dutt, Nikil ^c  

^a University of California Riverside   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c Ringgold Standard Institution Informatics   (United States)

Author keywords

Architecture tuning; Cache exploration; Cache hierarchy; Cache optimization; Configurable cache; Embedded systems; Low energy; Low power

Indexed keywords

ENERGY UTILIZATION; OPTIMIZATION; PERFORMANCE; POWER ELECTRONICS;

ARCHITECTURE TUNING; CACHE OPTIMIZATION; CONFIGURABLE CACHE; LOW ENERGY; LOW POWER;

BUFFER STORAGE;

EID: 28444456069     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/lpe.2005.195540     Document Type: Conference Paper

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