A 2.6psrms-period-jitter 900MHz all-digital fractional-N PLL built with standard cells

European Solid-State Circuits Conference

Volumn , Issue , 2011, Pages 455-458

  Su, Richard ^a   Lanzisera, Steven ^a,b   Pister, Kristofer S J ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b LAWRENCE BERKELEY NATIONAL LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK SKEWS; DIFFERENT PROCESS; DIGITAL BLOCKS; DIGITAL CORRECTION; DIGITAL SYNTHESIS; FRACTIONAL-N; FRACTIONAL-N PHASE-LOCKED LOOPS; JITTER PERFORMANCE; MULTI-PATH; STANDARD CELL; TIME TO DIGITAL CONVERTERS;

CELLS; DELAY CIRCUITS; ELECTRIC BATTERIES; FREQUENCY CONVERTERS; PHASE LOCKED LOOPS; STANDARDS;

JITTER;

EID: 82955241258     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2011.6045005     Document Type: Conference Paper

References (10)

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