Design of CMOS Adaptive-Bandwidth PLL/DLLs: A General Approach

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 50, Issue 11, 2003, Pages 860-869

  Kim, Jaeha ^a   Horowitz, Mark A ^b   Wei, Gu Yeon ^c  

^a Seoul National University   (South Korea)

^b Stanford University   (United States)

^c HARVARD UNIVERSITY   (United States)

Author keywords

Adaptive bandwidth; Delay locked loop (DLL); Phase locked loop (PLL)

Indexed keywords

BANDWIDTH; CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; ELECTRIC POTENTIAL; ELECTRIC RESISTANCE; FREQUENCIES; GAIN MEASUREMENT; PRODUCT DESIGN;

ADAPTIVE BANDWIDTH; DELAY-LOCKED LOOPS (DLL);

PHASE LOCKED LOOPS;

EID: 0345293104     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSII.2003.819120     Document Type: Article

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