Bang-bang digital PLLS at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2009, Pages

  Rylyakov, A ^a   Tierno, J ^a   Ainspan, H ^a   Plouchart, J O ^a   Bulzacchelli, J ^a   Deniz, Z Toprak ^a   Friedman, D ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 70349294340     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2009.4977324     Document Type: Conference Paper

References (8)

1. R.B. Staszewski, J.L. Wallberg, S. Rezeq, et al., "All-Digital PLL and Transmitter forMobile Phones, " IEEE J. Solid State Circuits, vol. 40, no. 12, pp. 2469-2482, Dec., 2005.
2. C.-M. Hsu, M.Z. Straayer, and M.H. Perrott, "A Low-Noise, Wide-BW 3.6GHz DigitalΔΣ Fractional-N Frequency Synthesizer with a Noise-Shaping Time-to-Digital Converterand Quantization Noise Cancellation, " ISSCC Dig. Tech. Papers, pp. 340-341, Feb., 2008.
3. C. Weltin-Wu, E. Temporiti, D. Baldi, and F. Svelto, "A 3GHz Fractional-N All-DigitalPLL with Precise Time-to-Digital Converter Calibration and Mismatch Correction, " ISSCCDig. Tech. Papers, pp. 344-345, Feb., 2008.
4. J.A. Tierno, A.V. Rylyakov, and D. Friedman, "A Wide Power Supply Range, WideTuning Range, All Static CMOS All Digital PLL in 65 nm SOI", IEEE J. Solid -State Circuits, vol. 43, no. 1, pp. 42-51, Jan., 2008.
5. N. Da Dalt, "Theory and Implementation of Digital Bang-Bang Frequency Synthesizersfor High Speed Serial Data Communications", Diplom-Ingenieur Dissertation, Feb., 2007.
6. P.K. Hanomolu, G.-Y. Wei, U.-K. Moon, and K. Mayaram, "Digitally-Enhanced Phase-Locking Circuits, " IEEE Custom Integrated Circuits Conf., pp. 361-368, Sept., 2007.
7. A.V. Rylyakov, J.A. Tierno, D.Z. Turker, et al. "A Modular All-Digital PLL ArchitectureEnabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS, " ISSCC Dig. Tech.Papers, pp. 516-517, Feb. 2008.
8. J. Lee, K.S. Kundert, and B. Razavi, "Analysis and Modeling of Bang-Bang Clock andData Recovery Circuits, " IEEE J. Solid-State Circuits, vol. 39, 9, pp. 1571-1580, Sept., 2004.