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Volumn , Issue , 2011, Pages 275-278

A standard cell based all-digital time-to-digital converter with reconfigurable resolution and on-line background calibration

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL DESIGNS; OVER SAMPLING; PROTOTYPE CHIP; RE-CONFIGURABLE; STANDARD-CELL; TIME TO DIGITAL CONVERTERS;

EID: 82955214026     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2011.6044960     Document Type: Conference Paper
Times cited : (8)

References (12)
  • 2
    • 49549111168 scopus 로고    scopus 로고
    • A Low-Noise, Wide-BW 3.6 GHz, Fractional-N Frequency Synthesizer with a Noise Shaping Time-to-Digital Converter and Quantization Noise Cancellation
    • Feb
    • C-M. Hsu, M.Z. Straayer, M.H. Perrot, "A Low-Noise, Wide-BW 3.6 GHz, Fractional-N Frequency Synthesizer with a Noise Shaping Time-to-Digital Converter and Quantization Noise Cancellation", ISSCC Dig.Tech.Papers, pp 340-341, Feb, 2008
    • (2008) ISSCC Dig.Tech.Papers , pp. 340-341
    • Hsu, C.-M.1    Straayer, M.Z.2    Perrot, M.H.3
  • 3
    • 77952137360 scopus 로고    scopus 로고
    • A 86 MHz-to-12 GHz Digital-Intensive Phase-Modulated Fractional-N PLL using a 15 pJ/shot 5 ps TDC in 40 nm digital CMOS
    • Feb
    • J. Borremans, K. Vengattaramane, V. Gianinni, J. Craninckx, "A 86 MHz-to-12 GHz Digital-Intensive Phase-Modulated Fractional-N PLL using a 15 pJ/shot 5 ps TDC in 40 nm digital CMOS", ISSCC Dig.Tech.Papers, pp 480-481, Feb, 2010
    • (2010) ISSCC Dig.Tech.Papers , pp. 480-481
    • Borremans, J.1    Vengattaramane, K.2    Gianinni, V.3    Craninckx, J.4
  • 4
    • 61449204062 scopus 로고    scopus 로고
    • A 3 GHz Fractional All-Digital PLL with a 1.8 MHz Bandwidth Implementing Spur Reduction Technqiues
    • March
    • E. Temporiti, C. Weltin-Wu, D. Baldi, R. Tonietto, F. Svelto, "A 3 GHz Fractional All-Digital PLL with a 1.8 MHz Bandwidth Implementing Spur Reduction Technqiues", J. Solid State Circuits, vol.44, no. 3, pp. 824-834, March 2009.
    • (2009) J. Solid State Circuits , vol.44 , Issue.3 , pp. 824-834
    • Temporiti, E.1    Weltin-Wu, C.2    Baldi, D.3    Tonietto, R.4    Svelto, F.5
  • 5
    • 41549133070 scopus 로고    scopus 로고
    • A 9 b, 1.25 ps resolution coarse-fine time-to-digital converter in 90 nm CMOS that amplifies a time residue
    • DOI 10.1109/JSSC.2008.917405
    • M. Lee, A. A. Abidi, "A 9 b, 1.25 ps Resolution Coarse-Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue", J. Solid State Circuits, Vol.43, No.4, pp 769-777, April 2008. (Pubitemid 351464069)
    • (2008) IEEE Journal of Solid-State Circuits , vol.43 , Issue.4 , pp. 769-777
    • Lee, M.1    Abidi, A.A.2
  • 6
    • 46749156902 scopus 로고    scopus 로고
    • A Local Passive Time Interpolation Concept for Variation-Tolerant High-Resolution Time-to-Digital Conversion
    • July
    • S. Henzler, S. Koeppe, D. Lorenz, W. Kamp, R. Kuenemund, and D.Schmitt-Landsiedel,"A Local Passive Time Interpolation Concept for Variation-Tolerant High-Resolution Time-to-Digital Conversion", J. Solid State Circuits, Vol.43, No.7, pp 1666-1676, July 2008.
    • (2008) J. Solid State Circuits , vol.43 , Issue.7 , pp. 1666-1676
    • Henzler, S.1    Koeppe, S.2    Lorenz, D.3    Kamp, W.4    Kuenemund, R.5    Schmitt-Landsiedel, D.6
  • 7
    • 33746623994 scopus 로고    scopus 로고
    • A CMOS time-to-digital converter with better than 10 ps single-shot precision
    • DOI 10.1109/JSSC.2006.874281, 1637593
    • J-P Jansson, A. Mantyniemi, and J. Kostamovaara, "A CMOS Time-to-Digital Converter With Better Than 10 ps Single-Shot Precision", J. Solid State Circuits, Vol.41, No.6, pp.1286-1296, June 2006. (Pubitemid 44143865)
    • (2006) IEEE Journal of Solid-State Circuits , vol.41 , Issue.6 , pp. 1286-1296
    • Jansson, J.-P.1    Mantyniemi, A.2    Kostamovaara, J.3
  • 8
    • 76249100318 scopus 로고    scopus 로고
    • A Gated Ring Oscillator Based Parallel-TDC System with Digital Resolution Enhancement
    • November
    • K. Vengattaramane, J. Borremans, M. Steyaert and J. Craninckx, "A Gated Ring Oscillator Based Parallel-TDC System With Digital Resolution Enhancement", Proc. A-SSCC., pp. 57-60. November 2009.
    • (2009) Proc. A-SSCC , pp. 57-60
    • Vengattaramane, K.1    Borremans, J.2    Steyaert, M.3    Craninckx, J.4
  • 9
    • 77952162025 scopus 로고    scopus 로고
    • A 2.1 to 2.8 GHz All-Digital Frequency Synthesizer with a Time-Windowed TDC
    • Feb
    • Takashi Tokairin, Mitsuji Okada, Masaki Kitsunezuka, Tadashi Maeda, Muneo Fukaishi, "A 2.1 to 2.8 GHz All-Digital Frequency Synthesizer with a Time-Windowed TDC", ISSCC Dig. Tech. Papers, pp. 470-471, Feb 2010.
    • (2010) ISSCC Dig. Tech. Papers , pp. 470-471
    • Tokairin, T.1    Okada, M.2    Kitsunezuka, M.3    Maeda, T.4    Fukaishi, M.5
  • 10
    • 77952185282 scopus 로고    scopus 로고
    • A Calibration Free 800 MHz Fractional-N Digital PLL with Embedded TDC
    • Feb
    • Mike Shuo-Wei Chen, David Su, Srenik Mehta, "A Calibration Free 800 MHz Fractional-N Digital PLL with Embedded TDC", ISSCC Dig. Tech. Papers, pp. 472-473, Feb 2010.
    • (2010) ISSCC Dig. Tech. Papers , pp. 472-473
    • Chen, M.S.-W.1    Su, D.2    Mehta, S.3
  • 11
    • 77949351332 scopus 로고    scopus 로고
    • Time-to-Digital Converter for frequency synthesis based on Digital Bang-Bang DLL
    • March
    • Marco Zanuso, Paolo Madoglio,Salvatore Levantino, Carlo Samori, Andrea Lacaita,"Time-to-Digital Converter for frequency synthesis based on Digital Bang-Bang DLL", IEEE Trans. On Circuits and Systems-I, Vol.57, No.3,pp 548-555, March 2010
    • (2010) IEEE Trans. on Circuits and Systems-I , vol.57 , Issue.3 , pp. 548-555
    • Zanuso, M.1    Madoglio, P.2    Levantino, S.3    Samori, C.4    Lacaita, A.5
  • 12
    • 84865431137 scopus 로고    scopus 로고
    • A 3 MHz Bandwidth Low Noise RF All Digital PLL with 12 ps Resolution Time-to-Digital Converter
    • September
    • R. Tonietto, E. Zuffeti, R. Castello, I. Bietti,"A 3 MHz Bandwidth Low Noise RF All Digital PLL with 12 ps Resolution Time-to-Digital Converter", Proc. ESSCIRC, pp 150-153, September 2006
    • (2006) Proc. ESSCIRC , pp. 150-153
    • Tonietto, R.1    Zuffeti, E.2    Castello, R.3    Bietti, I.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.