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A 86 MHz-to-12 GHz Digital-Intensive Phase-Modulated Fractional-N PLL using a 15 pJ/shot 5 ps TDC in 40 nm digital CMOS
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Feb
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J. Borremans, K. Vengattaramane, V. Gianinni, J. Craninckx, "A 86 MHz-to-12 GHz Digital-Intensive Phase-Modulated Fractional-N PLL using a 15 pJ/shot 5 ps TDC in 40 nm digital CMOS", ISSCC Dig.Tech.Papers, pp 480-481, Feb, 2010
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A 3 GHz Fractional All-Digital PLL with a 1.8 MHz Bandwidth Implementing Spur Reduction Technqiues
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E. Temporiti, C. Weltin-Wu, D. Baldi, R. Tonietto, F. Svelto, "A 3 GHz Fractional All-Digital PLL with a 1.8 MHz Bandwidth Implementing Spur Reduction Technqiues", J. Solid State Circuits, vol.44, no. 3, pp. 824-834, March 2009.
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A 9 b, 1.25 ps resolution coarse-fine time-to-digital converter in 90 nm CMOS that amplifies a time residue
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M. Lee, A. A. Abidi, "A 9 b, 1.25 ps Resolution Coarse-Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue", J. Solid State Circuits, Vol.43, No.4, pp 769-777, April 2008. (Pubitemid 351464069)
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A Local Passive Time Interpolation Concept for Variation-Tolerant High-Resolution Time-to-Digital Conversion
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S. Henzler, S. Koeppe, D. Lorenz, W. Kamp, R. Kuenemund, and D.Schmitt-Landsiedel,"A Local Passive Time Interpolation Concept for Variation-Tolerant High-Resolution Time-to-Digital Conversion", J. Solid State Circuits, Vol.43, No.7, pp 1666-1676, July 2008.
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A CMOS time-to-digital converter with better than 10 ps single-shot precision
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J-P Jansson, A. Mantyniemi, and J. Kostamovaara, "A CMOS Time-to-Digital Converter With Better Than 10 ps Single-Shot Precision", J. Solid State Circuits, Vol.41, No.6, pp.1286-1296, June 2006. (Pubitemid 44143865)
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A Gated Ring Oscillator Based Parallel-TDC System with Digital Resolution Enhancement
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K. Vengattaramane, J. Borremans, M. Steyaert and J. Craninckx, "A Gated Ring Oscillator Based Parallel-TDC System With Digital Resolution Enhancement", Proc. A-SSCC., pp. 57-60. November 2009.
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A 2.1 to 2.8 GHz All-Digital Frequency Synthesizer with a Time-Windowed TDC
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Takashi Tokairin, Mitsuji Okada, Masaki Kitsunezuka, Tadashi Maeda, Muneo Fukaishi, "A 2.1 to 2.8 GHz All-Digital Frequency Synthesizer with a Time-Windowed TDC", ISSCC Dig. Tech. Papers, pp. 470-471, Feb 2010.
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A Calibration Free 800 MHz Fractional-N Digital PLL with Embedded TDC
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Mike Shuo-Wei Chen, David Su, Srenik Mehta, "A Calibration Free 800 MHz Fractional-N Digital PLL with Embedded TDC", ISSCC Dig. Tech. Papers, pp. 472-473, Feb 2010.
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77949351332
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Time-to-Digital Converter for frequency synthesis based on Digital Bang-Bang DLL
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Marco Zanuso, Paolo Madoglio,Salvatore Levantino, Carlo Samori, Andrea Lacaita,"Time-to-Digital Converter for frequency synthesis based on Digital Bang-Bang DLL", IEEE Trans. On Circuits and Systems-I, Vol.57, No.3,pp 548-555, March 2010
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12
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A 3 MHz Bandwidth Low Noise RF All Digital PLL with 12 ps Resolution Time-to-Digital Converter
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R. Tonietto, E. Zuffeti, R. Castello, I. Bietti,"A 3 MHz Bandwidth Low Noise RF All Digital PLL with 12 ps Resolution Time-to-Digital Converter", Proc. ESSCIRC, pp 150-153, September 2006
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