A 12fJ/conversion-step 8bit 10MS/s asynchronous SAR ADC for low energy radios

ESSCIRC 2010 - 36th European Solid State Circuits Conference

Volumn , Issue , 2010, Pages 214-217

  Harpe, Pieter ^a   Zhou, Cui ^a   Wang, Xiaoyan ^a   Dolmans, Guido ^a   De Groot, Harmke ^a  

^a HOLST CENTRE   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

90NM CMOS; ASYNCHRONOUS DYNAMICS; DYNAMIC DESIGN; LOW ENERGIES; LOW-COMPLEXITY; POWER EFFICIENCY; SAMPLING FREQUENCIES; SAR ADC; STANDBY POWER;

CMOS INTEGRATED CIRCUITS;

OPTIMIZATION;

EID: 78650391095     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2010.5619891     Document Type: Conference Paper

References (6)

1. P. Harpe, C. Zhou, X. Wang, G. Dolmans, and H. de Groot, "A 30fJ/Conversion-Step 8b 0-to-10MS/s asynchronous SAR ADC in 90nm CMOS," ISSCC Dig. Tech. Papers, pp. 388-389, Feb. 2010.
2. J. McCreary and P. Gray, "All-MOS charge redistribution analog-to-digital conversion techniques - part I," IEEE J. Solid-State Circuits, vol. 10, no. 6, pp. 371-379, Dec. 1975.
3. M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and B. Nauta, "A 1.9μW 4.4fJ/conversion-step 10b 1MS/s charge-redistribution ADC," ISSCC Dig. Tech. Papers, pp. 244-245, Feb. 2008.
4. B. Murmann. (2010, Feb.) ADC performance survey 1997-2010. [Online]. Available: http://www.stanford.edu/~murmann/adcsurvey.html
5. C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, "A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process," Symposium on VLSI Circuits, pp. 236-327, 2009.
6. C.-C. Liu, S.-J. Chang, G.-Y. Huang, Y.-Z. Lin, C.-M. Huang, C.-H. Huang, L. Bu, and C.-C. Tsai, "A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation," ISSCC Dig. Tech. Papers, pp. 386-387, Feb. 2010.