Energy-efficient reconfigurable computing using a circuit-architecture- software co-design approach

IEEE Journal on Emerging and Selected Topics in Circuits and Systems

Volumn 1, Issue 3, 2011, Pages 369-380

  Paul, Somnath ^a   Chatterjee, Subho ^b   Mukhopadhyay, Saibal ^b   Bhunia, Swarup ^a  

^a Case Western Reserve University   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Asymmetric memory; content aware mapping; low power; reconfigurable hardware

Indexed keywords

APPLICATION MAPPING; ASYMMETRIC MEMORY; CO-DESIGN APPROACH; CO-DESIGNS; COMPLEMENTARY METAL OXIDE SEMICONDUCTORS; COMPUTING ELEMENT; CONTENT-AWARE; DESIGN FLOWS; DESIGN SOLUTIONS; ENERGY DELAY PRODUCT; ENERGY EFFICIENT; LOGIC STATE; LOW POWER; MEMORY ACCESS PATTERNS; MEMORY CELL; MEMORY CELL DESIGN; MEMORY TECHNOLOGY; MULTITHRESHOLD; NANO SCALE; PROGRAMMABLE INTERCONNECTS; PROPOSED ARCHITECTURES; RANDOM ACCESS MEMORIES; RE-CONFIGURABLE; READ PERFORMANCE; RECONFIGURABLE COMPUTING; RECONFIGURABLE COMPUTING ARCHITECTURE; SPATIO-TEMPORAL; SPIN TORQUE TRANSFER; STATIC RANDOM ACCESS MEMORY; TRADE OFF; VOLTAGE-SCALING;

CELLS; COMPUTER HARDWARE; DESIGN; ENERGY EFFICIENCY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); MAPPING; MEMORY ARCHITECTURE; MIMO SYSTEMS; RECONFIGURABLE HARDWARE; SEMICONDUCTOR STORAGE; SOFTWARE ARCHITECTURE;

STATIC RANDOM ACCESS STORAGE;

EID: 81255149500     PISSN: 21563357     EISSN: None     Source Type: Journal    
DOI: 10.1109/JETCAS.2011.2165232     Document Type: Article

References (32)

1. K. Compton and S. Hauck, "Reconfigurable computing: A survey of systems and software," ACM Comput. Surv., vol. 34, no. 2, pp. 171-210, 2002.
2. V. Betz, J. Rose, and A. Marquardt, Architecture and CAD for Deep-Submicron FPGAs. New York: Springer, 1999.
3. A. P. Chandrakasan, A. Rahman, S. Das, and R. Reif, "Wiring requirement and three-dimensional integration technology for field programmable gate arrays," IEEE Trans. Very Large Scale (VLSI) Syst., vol. 11, no. 1, pp. 44-54, Feb. 2003.
4. J. Cong and S. Xu, "Technology mapping for FPGAs with embedded memory blocks," in Int. Symp. Field-Programmable Gate Arrays, 1998, pp. 179-188.
5. S. J. E. Wilton, "MAP: Heterogeneous technology mapping for area reduction in FPGAs with embedded memory arrays," in Int. Symp. Field-Programmable Gate Arrays, 1998, pp. 171-178.
6. J. Cong and S. Xu, "Performance-driven technology mapping for heterogeneous FPGAs," IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. 19, no. 11, pp. 1268-1281, Nov. 2000.
7. D. Jones and D. M. Lewis, "A time-multiplexed FPGA architecture for logic evaluation," in Proc. Custom Integrated Circuits Conf., 1995, pp. 495-498.
8. S. Paul and S. Bhunia, "MBARC: A scalable memory based reconfigurable computing framework for nanoscale devices," in Proc. Asia South Pacific Design Automat. Conf., 2008, pp. 77-82.
9. S. Paul and S. Bhunia, "Reconfigurable computing using content addressable memory for improved performance and resource usage," in Design Automat. Conf., 2008, pp. 786-791.
10. S. Paul, S. Chatterjee, S. Mukhopadhyay, and S. Bhunia, "Nanoscale reconfigurable computing using non-volatile 2-D STTRAM array," in Proc. Int. Conf. Nanotechnol. Arrays, 1998, pp. 880-883.
11. S. Paul, S. Chatterjee, S. Mukhopadhyay, and S. Bhunia, "A circuit-software co-design approach for improving EDP in reconfigurable frameworks," in Int. Conf. Comput. Aided Design, 2009, pp. 109-112.
12. J. Singh et al., "Single ended static random access memory for low-vdd, high-speed embedded systems," in Int. Conf. VLSI Design, 2009, pp. 307-312.
13. L. Chang et al., "Stable SRAM cell design for the 32 nm node and beyond," in Proc. Int. Symp. VLSI Technol., 2005, pp. 128-129.
14. S. Mukhopadhyay, H. Mahmoodi, and K. Roy, "Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS," IEEE Trans. Computer-Aided Design Integrated Circuits Syst., vol. 24, no. 12, pp. 1859-1880, Dec. 2005.
15. Predictive tech. model (PTM) [Online]. Available: http://www.eas.asu. edu/~ptm
16. Placement and Routing for FPGAs v4.3 VPR & T-VPack: Versatile Packing [Online]. Available: http://www.eecg.toronto.edu/~vaughn/ vpr/vpr.html
17. Intelligent FPGA Architecture Repository [Online]. Available: http:// www.eecg.utoronto.ca/vpr/architectures/.
18. VPR Package for FPGA power estimation [Online]. Available: http:// www.ece.ubc.ca/~stevew/powermodel.html.
19. G. Karypis et al., "Multilevel hypergraph partitioning: Applications in VLSI domain," IEEE Trans. Very Large Scale (VLSI) Syst., vol. 7, no. 1, pp. 69-79, Mar. 1999.
20. J. Cong and Y. Ding, "FlowMap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs," IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. 13, no. 1, pp. 1-12, Jan. 1994.
21. M. Hosomi et al., "A novel non-volatile nemory with spin torque transfer magnetization switching: Spin-RAM," in Proc. Int. Electron Devices Meeting, 2005, pp. 459-462.
22. T. Kawahara et al., "2 Mb Spin-Transfer Torque RAM (SPRAM) with bit-by-bit bidirectional current write and parallelizing-direction current read," Int. J. Solid-State Circuits, vol. 43, no. 1, pp. 109-120, 2007.
23. J. Hayakawa et al., "Current-driven magnetization switching in CoFeB/ MgO/CoFeB magnetic tunnel junctions," Jpn. J. Appl. Phys., vol. 44, no. 41, pp. L1267-L1270, 2005.
24. S. Tehrani et al., "Magnetoresistive random access memory using magnetic tunnel junctions," Proc. IEEE, vol. 91, no. 5, pp. 703-714, May 2003.
25. ITRS 2007: Emerging research devices [Online]. Available: http://www.itrs.net/Links/2007ITRS/2007-Chapters/2007-ERD.pdf
26. V. K. Prasanna, "Energy efficient computations on FPGAs," J. Supercomput., vol. 32, no. 2, pp. 139-162, 2005.
27. F. Li, Y. Lin, L. He, and J. Cong, "Low-power FPGA using pre-defined Dual-Vdd/Dual-Vt fabrics," in Int. Symp. Field Programmable Gate Arrays, 2004, pp. 42-50.
28. R.Williams, "How we found the missing memristor," IEEE Spectrum, vol. 45, no. 12, pp. 28-35, Dec. 2008.
29. W. Y. Cho et al., "A 0.18-μm 3.0 V 64-Mb non-volatile phase transition random access memory (PRAM)," IEEE J. Solid State Circuits, vol. 40, no. 1, pp. 293-300, 2005.
30. D. Lewis and G. Lemieux, "Circuit design of routing switches," in Proc. Int. Symp. Field Programmable Gate Arrays, 2002, pp. 19-28.
31. Cacti 5.1 Tech. Rep. [Online]. Available: http://www.hpl.hp.com/ techreports/2008/HPL-2008-20.pdf
32. K. Zhang, U. Bhattacharya, Z. Chen, F. Hamzaoglu, D. Murray, N. Vallepalli, Y.Wang, B. Zheng, and M. Bohr, "A 3-GHz 70-Mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply," IEEE J. Solid State Circuits, vol. 41, no. 1, pp. 146-151, Jan. 2006.